Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

VPR error when using PLLE2_BASE in a design #2123

Open
carlosedp opened this issue Apr 15, 2021 · 5 comments
Open

VPR error when using PLLE2_BASE in a design #2123

carlosedp opened this issue Apr 15, 2021 · 5 comments

Comments

@carlosedp
Copy link

While running a design that uses PLLE2_BASE, VPR returns the error:

Message: Failed to find matching architecture model for 'PLLE2_BASE'

My design has:

...
   PLLE2_BASE
    #(.BANDWIDTH            ("OPTIMIZED"),
        .STARTUP_WAIT         ("FALSE"),
        .DIVCLK_DIVIDE        (4),
        .CLKFBOUT_MULT        (33),
        .CLKFBOUT_PHASE       (0.000),
        .CLKOUT0_DIVIDE       (33),
        .CLKOUT0_PHASE        (0.000),
        .CLKOUT0_DUTY_CYCLE   (0.500),
        .CLKIN1_PERIOD        (10.000))
   PLLE2_BASE_inst
     (.CLKOUT0(clko),
      .CLKOUT1(),
      .CLKOUT2(),
      .CLKOUT3(),
      .CLKOUT4(),
      .CLKOUT5(),
      .CLKFBOUT(clkfb),
      .LOCKED(lock),
      .CLKIN1(clki),
      .PWRDWN(1'b0),
      .RST(1'b0),
      .CLKFBIN(clkfb));
...

My installation follows the packeges listed on https://symbiflow-examples.readthedocs.io/en/latest/getting-symbiflow.html#prerequisites
@WhiteNinjaZ
Copy link

WhiteNinjaZ commented Aug 26, 2021 •
edited
Loading

@acomodi @mkurc-ant I also get this VPR error message Failed to find matching architecture model for 'PLLE2_BASE when trying to implement the PLLE2_BASE primitive in my designs. Yosys builds correctly, its just VPR that has issues.

@mkurc-ant
Copy link
Collaborator

@WhiteNinjaZ It looks like the techmap for PLLE2_BASE does not match the actual PLLE2_BASE primitive emitted by Yosys. Could you verify that? The techmap is there https://github.com/SymbiFlow/symbiflow-arch-defs/blob/709cac7866d96acfaffa186746dc12c713461fcb/xc/xc7/techmap/cells_map.v#L4151-L4167 You should find the corresponding cell model in Yosys

@WhiteNinjaZ
Copy link

@mkurc-ant Here is the techmap in yosys cells_xtra.v:


module PLLE2_BASE (...);
    parameter BANDWIDTH = "OPTIMIZED";
    parameter integer CLKFBOUT_MULT = 5;
    parameter real CLKFBOUT_PHASE = 0.000;
    parameter real CLKIN1_PERIOD = 0.000;
    parameter integer CLKOUT0_DIVIDE = 1;
    parameter real CLKOUT0_DUTY_CYCLE = 0.500;
    parameter real CLKOUT0_PHASE = 0.000;
    parameter integer CLKOUT1_DIVIDE = 1;
    parameter real CLKOUT1_DUTY_CYCLE = 0.500;
    parameter real CLKOUT1_PHASE = 0.000;
    parameter integer CLKOUT2_DIVIDE = 1;
    parameter real CLKOUT2_DUTY_CYCLE = 0.500;
    parameter real CLKOUT2_PHASE = 0.000;
    parameter integer CLKOUT3_DIVIDE = 1;
    parameter real CLKOUT3_DUTY_CYCLE = 0.500;
    parameter real CLKOUT3_PHASE = 0.000;
    parameter integer CLKOUT4_DIVIDE = 1;
    parameter real CLKOUT4_DUTY_CYCLE = 0.500;
    parameter real CLKOUT4_PHASE = 0.000;
    parameter integer CLKOUT5_DIVIDE = 1;
    parameter real CLKOUT5_DUTY_CYCLE = 0.500;
    parameter real CLKOUT5_PHASE = 0.000;
    parameter integer DIVCLK_DIVIDE = 1;
    parameter real REF_JITTER1 = 0.010;
    parameter STARTUP_WAIT = "FALSE";
    output CLKFBOUT;
    output CLKOUT0;
    output CLKOUT1;
    output CLKOUT2;
    output CLKOUT3;
    output CLKOUT4;
    output CLKOUT5;
    output LOCKED;
    input CLKFBIN;
    input CLKIN1;
    input PWRDWN;
    input RST;
endmodule

Is that what you were talking about? If so it looks like the arch-def techmap is missing a PWRDWN input. There are also a few differences in the parameters.

@mkurc-ant
Copy link
Collaborator

@WhiteNinjaZ Yes that's it. The port is missing in the techmap so Yosys does not apply it. This is the problem I'll create a PR with a fix for that tomorrow.

@mkurc-ant
Copy link
Collaborator

mkurc-ant commented Aug 27, 2021 •
edited
Loading

After some digging I found an issue about that (#1991) and a PR with a fix (#2007). The PR failed in CI but the cause should be fixed now so I have rebased it. Hopefully it gets green

@alanvgreen alanvgreen mentioned this issue Oct 29, 2022
Closed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
3 participants
@carlosedp @mkurc-ant @WhiteNinjaZ