In order to have an easier debugging of specific cells, it might be useful to add to the device database a cells/bel exclusion map, so that the P&R tool is forbidden to use certain bels during placement.

An example would involve xc7 devices be the FFs cell types which can be placed in different BELs, belonging to different sites, in this case, SLICEs, ILOGIC, OLOGIC.

If for instance the LUT-thrus to FFs in a slice need to be debugged, or for any other reason involving the strict placement of FFs into SLICELs (still for debugging purposes), there should be a mechanism to avoid placing those cells in certain BELs.

Possible solution

Add to the device schema a cell/bel exclusion map and add a device patching step (the P&R tool should also be aware of this and, in case of nextpnr, the chip info should probably be changed as well).

cc @gatecat