PR #111 adds various LiteX examples for arty-35 and arty-100.

Each example implements a different CPU core type, and #111 currently adds picorv32 and VecRiscv.

There are other CPU-types that can be implemented.

With fixes in the toolchain/tools

• minerva: This requires xc7: yosys: allow custom top module instead of using only auto-top f4pga/f4pga-arch-defs#1906 to be merged. The problem is that the minerva core has a yosys attribute which sets the top-level module to be the minerva core. With the -auto-top parameter when getting the hierarchy is used, the real top module gets discarded in favour of the minerva one.
• serv: There is a .vh file which makes yosys fail due to the fact that it cannot guess the frontend for it. To solve this we need to provide the -f verilog option when calling yosys. It should be fixed in symbiflow-arch-defs
• rocket: This currently fails during the VPR clean circuit step. The resulting synthesized design is big enough to let VPR consume all RAM available (16GB on my local machine) during the clean circuit step. This requires a proper fix in VPR

Requires some additional tools

• microwatt: This requires the usage of the VHDL plugin for yosys, as well as the powerpc64le-linux cross compilation toolchain.
• mor1kx: This requires the or1k-elf binariy to compile the bios
• lm32: This requires the lm32-elf binary to compile the bios
• cv32e40p: This core is written in SystemVerilog. Unsure if it is simple enough to get it through yosys