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Why are you not using yield mem[0].eq(0x5432123412345678) in pysim-only code?
It was like that in the original test code for some reason. I wrongly assumed it was deliberately working around a nMigen restriction.
Also, I foolishly looked for a __setitem__ in Memory. I now realize I don't really need it, just to call eq on it.
Revised test below:
fromnmigenimportModule, Memoryfromnmigen.simimportSimulatorm=Module()
mem=Memory(width=64, depth=8)
rdport=mem.read_port()
m.submodules.rdport=rdportdefprocess():
yieldmem[0].eq(0x5432123412345678)
yield# both cxxsim and pysim passesassert (yieldmem[0]) ==0x5432123412345678# only pysim passesassert (yieldrdport.data) ==0x5432123412345678forenginein ["pysim", "cxxsim"]:
sim=Simulator(m, engine=engine)
sim.add_clock(1e-6)
sim.add_sync_process(process)
sim.run()
print(f"Engine {engine} OK.")
We currently use code similar to this, in PySim, to re-initialize the memory state in one go, before a sub-test:
I suppose it's not really a CXXSim bug, since we shouldn't really be writing to some private Memory array. More of a feature request, I guess.
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