I tried to run post-synthesis functional simulation for the conter_arty test in xc7/tests by Modelsim. And I found that only the wave of led[0] was correct, other 7 led wires were always 0 (see Fig.1).

The only difference from your original test is modifying the verilog file to add a reset function. The code is as follows:

`module top (
input wire clk,

input  wire [7:0] sw,
output wire [7:0] led

);

localparam BITS = 8;
localparam LOG2DELAY = 28;

reg [BITS+LOG2DELAY-1:0] counter = 0;

always @(posedge clk) begin
    if(!sw[0])
        counter <= 0;
    else
	    counter <= counter + 1;
end

assign led[7:0] = counter[7:0];

endmodule`

The post-synthesis file was generated by VPR, and the work libraries were symbiflow-arch-defs/vpr/primitives.v and symbiflow-arch-defs/xc/xc7/techmap/cells_sim.v.

Is there something wrong with the simulation cells? Or is there something wrong with the simulation process?