Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: azonenberg/starshipraider
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: db6c8083cdef
Choose a base ref
...
head repository: azonenberg/starshipraider
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 205ad0463961
Choose a head ref
  • 1 commit
  • 4 files changed
  • 1 contributor

Commits on Dec 28, 2020

  1. Verified

    This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
    Copy the full SHA
    205ad04 View commit details
Showing with 2,992 additions and 36 deletions.
  1. +3 −0 boards/probes/akl-ad1/.gitignore
  2. +2,740 −1 boards/probes/akl-ad1/akl-ad1.kicad_pcb
  3. +228 −20 boards/probes/akl-ad1/akl-ad1.pro
  4. +21 −15 boards/probes/akl-ad1/akl-ad1.sch
3 changes: 3 additions & 0 deletions boards/probes/akl-ad1/.gitignore
Original file line number Diff line number Diff line change
@@ -1,2 +1,5 @@
output/*.gbr
output/*.zip
output/*.drl
*-bak
*cache*
2,741 changes: 2,740 additions & 1 deletion boards/probes/akl-ad1/akl-ad1.kicad_pcb

Large diffs are not rendered by default.

248 changes: 228 additions & 20 deletions boards/probes/akl-ad1/akl-ad1.pro
Original file line number Diff line number Diff line change
@@ -1,33 +1,241 @@
update=22/05/2015 07:44:53
update=Mon 28 Dec 2020 06:23:56 AM PST
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.125
MinViaDiameter=0.5499999999999999
MinViaDrill=0.25
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.31
TrackWidth2=0.31
ViaDiameter1=0.55
ViaDrill1=0.25
ViaDiameter2=0.55
ViaDrill2=0.25
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.05
SolderMaskMinWidth=0.05
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.15
TrackWidth=0.31
ViaDiameter=0.55
ViaDrill=0.25
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
36 changes: 21 additions & 15 deletions boards/probes/akl-ad1/akl-ad1.sch
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@ $Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title "AKL-AD1"
Date "2020-12-27"
Date "2020-12-28"
Rev "0.1"
Comp "Antikernel Labs"
Comment1 "Andrew D. Zonenberg"
@@ -19,7 +19,7 @@ U 1 1 5FE908C0
P 4950 3500
F 0 "J2" H 5050 3475 50 0000 L CNN
F 1 "901-10511-3" H 5050 3384 50 0000 L CNN
F 2 "" H 4950 3500 50 0001 C CNN
F 2 "azonenberg_pcb:CONN_SMA_EDGE_AMPHENOL_901_10511_3" H 4950 3500 50 0001 C CNN
F 3 "" H 4950 3500 50 0001 C CNN
1 4950 3500
1 0 0 -1
@@ -30,7 +30,7 @@ U 1 1 5FE90D04
P 1600 3550
F 0 "J1" H 1553 3888 50 0000 C CNN
F 1 "3211-60087" H 1553 3797 50 0000 C CNN
F 2 "" H 1600 3450 50 0001 C CNN
F 2 "azonenberg_pcb:CONN_SMPM_DUAL_AMPHENOL_3211-60087" H 1600 3450 50 0001 C CNN
F 3 "" H 1600 3450 50 0001 C CNN
1 1600 3550
-1 0 0 -1
@@ -41,7 +41,7 @@ U 1 1 5FE94CF5
P 2650 3750
F 0 "U1" H 3125 5025 50 0000 C CNN
F 1 "ADL5565" H 3125 4934 50 0000 C CNN
F 2 "" H 2650 3750 50 0001 C CNN
F 2 "azonenberg_pcb:QFN_16_0.5MM_3x3MM" H 2650 3750 50 0001 C CNN
F 3 "" H 2650 3750 50 0001 C CNN
1 2650 3750
1 0 0 -1
@@ -71,7 +71,7 @@ U 1 1 5FE97342
P 3750 3750
F 0 "R1" H 3820 3796 50 0000 L CNN
F 1 "49.9" H 3820 3705 50 0000 L CNN
F 2 "" V 3680 3750 50 0001 C CNN
F 2 "azonenberg_pcb:EIA_0402_RES_NOSILK" V 3680 3750 50 0001 C CNN
F 3 "" H 3750 3750 50 0001 C CNN
1 3750 3750
1 0 0 -1
@@ -115,7 +115,7 @@ U 1 1 5FE99455
P 2650 2150
F 0 "C1" H 2765 2196 50 0000 L CNN
F 1 "0.47 uF" H 2765 2105 50 0000 L CNN
F 2 "" H 2688 2000 50 0001 C CNN
F 2 "azonenberg_pcb:EIA_0402_CAP_NOSILK" H 2688 2000 50 0001 C CNN
F 3 "" H 2650 2150 50 0001 C CNN
1 2650 2150
1 0 0 -1
@@ -130,7 +130,7 @@ U 1 1 5FE9A0E9
P 3200 2150
F 0 "C2" H 3315 2196 50 0000 L CNN
F 1 "0.47 uF" H 3315 2105 50 0000 L CNN
F 2 "" H 3238 2000 50 0001 C CNN
F 2 "azonenberg_pcb:EIA_0402_CAP_NOSILK" H 3238 2000 50 0001 C CNN
F 3 "" H 3200 2150 50 0001 C CNN
1 3200 2150
1 0 0 -1
@@ -141,7 +141,7 @@ U 1 1 5FE9A44B
P 3750 2150
F 0 "C3" H 3865 2196 50 0000 L CNN
F 1 "0.47 uF" H 3865 2105 50 0000 L CNN
F 2 "" H 3788 2000 50 0001 C CNN
F 2 "azonenberg_pcb:EIA_0402_CAP_NOSILK" H 3788 2000 50 0001 C CNN
F 3 "" H 3750 2150 50 0001 C CNN
1 3750 2150
1 0 0 -1
@@ -152,7 +152,7 @@ U 1 1 5FE9A72C
P 4300 2150
F 0 "C5" H 4415 2196 50 0000 L CNN
F 1 "0.47 uF" H 4415 2105 50 0000 L CNN
F 2 "" H 4338 2000 50 0001 C CNN
F 2 "azonenberg_pcb:EIA_0402_CAP_NOSILK" H 4338 2000 50 0001 C CNN
F 3 "" H 4300 2150 50 0001 C CNN
1 4300 2150
1 0 0 -1
@@ -181,7 +181,7 @@ U 1 1 5FE9C4E4
P 4550 3150
F 0 "C6" H 4665 3196 50 0000 L CNN
F 1 "0.47 uF" H 4665 3105 50 0000 L CNN
F 2 "" H 4588 3000 50 0001 C CNN
F 2 "azonenberg_pcb:EIA_0402_CAP_NOSILK" H 4588 3000 50 0001 C CNN
F 3 "" H 4550 3150 50 0001 C CNN
1 4550 3150
1 0 0 -1
@@ -192,7 +192,7 @@ U 1 1 5FE9CEA6
P 4000 3150
F 0 "C4" H 4115 3196 50 0000 L CNN
F 1 "0.47 uF" H 4115 3105 50 0000 L CNN
F 2 "" H 4038 3000 50 0001 C CNN
F 2 "azonenberg_pcb:EIA_0402_CAP_NOSILK" H 4038 3000 50 0001 C CNN
F 3 "" H 4000 3150 50 0001 C CNN
1 4000 3150
1 0 0 -1
@@ -222,7 +222,7 @@ U 1 1 5FEA18D8
P 2650 1450
F 0 "C7" H 2765 1496 50 0000 L CNN
F 1 "4.7 uF" H 2765 1405 50 0000 L CNN
F 2 "" H 2688 1300 50 0001 C CNN
F 2 "azonenberg_pcb:EIA_0603_CAP_NOSILK" H 2688 1300 50 0001 C CNN
F 3 "" H 2650 1450 50 0001 C CNN
1 2650 1450
1 0 0 -1
@@ -237,7 +237,7 @@ U 1 1 5FEA1EE7
P 3200 1450
F 0 "C8" H 3315 1496 50 0000 L CNN
F 1 "22 uF" H 3315 1405 50 0000 L CNN
F 2 "" H 3238 1300 50 0001 C CNN
F 2 "azonenberg_pcb:EIA_1210_CAP_NOSILK" H 3238 1300 50 0001 C CNN
F 3 "" H 3200 1450 50 0001 C CNN
1 3200 1450
1 0 0 -1
@@ -252,7 +252,7 @@ U 1 1 5FEA3063
P 850 900
F 0 "J3" H 717 1200 50 0000 C CNN
F 1 "BARREL" H 717 1116 40 0000 C CNN
F 2 "" H 850 900 60 0000 C CNN
F 2 "azonenberg_pcb:CONN_CUI_PJ-058BH_HIPWR_BARREL_NOSLOT" H 850 900 60 0001 C CNN
F 3 "" H 850 900 60 0000 C CNN
1 850 900
-1 0 0 -1
@@ -263,9 +263,15 @@ U 1 1 5FEA3DDB
P 850 1500
F 0 "J4" H 717 1800 50 0000 C CNN
F 1 "BARREL" H 717 1716 40 0000 C CNN
F 2 "" H 850 1500 60 0000 C CNN
F 2 "azonenberg_pcb:CONN_CUI_PJ-058BH_HIPWR_BARREL_NOSLOT" H 850 1500 60 0001 C CNN
F 3 "" H 850 1500 60 0000 C CNN
1 850 1500
-1 0 0 -1
$EndComp
Text Label 2000 3400 0 50 ~ 0
IN_P
Text Label 2000 3700 0 50 ~ 0
IN_N
Text Label 4350 3500 0 50 ~ 0
VOUT
$EndSCHEMATC