gateware.uart: support words longer than 8-bits

It seems that the shift register was being truncated to 8-bits regardless of the requested word size, since the `data_bits` attribute was introduced in 0f497e4.
GlasgowEmbedded · Dec 29, 2020 · 41b1507 · 41b1507 · whitequark · Dec 29, 2020
1 parent f93bd48
commit 41b1507
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/software/glasgow/gateware/uart.py b/software/glasgow/gateware/uart.py
@@ -171,7 +171,7 @@ def calc_parity(sig, kind):
                 with m.State("DATA"):
                     with m.If(rx_stb):
                         m.d.sync += [
-                            rx_shreg.eq(Cat(rx_shreg[1:8], self.bus.rx_i)),
+                            rx_shreg.eq(Cat(rx_shreg[1:], self.bus.rx_i)),
                             rx_bitno.eq(rx_bitno + 1),
                         ]
                         with m.If(rx_bitno == rx_shreg.nbits - 1):
@@ -237,7 +237,7 @@ def calc_parity(sig, kind):
                     with m.If(tx_stb):
                         m.d.sync += [
                             self.bus.tx_o.eq(tx_shreg[0]),
-                            tx_shreg.eq(Cat(tx_shreg[1:8], C(0,1))),
+                            tx_shreg.eq(Cat(tx_shreg[1:], C(0,1))),
                         ]
                         m.next = "DATA"
                 with m.State("DATA"):
@@ -246,7 +246,7 @@ def calc_parity(sig, kind):
                         with m.If(tx_bitno != tx_shreg.nbits - 1):
                             m.d.sync += [
                                 self.bus.tx_o.eq(tx_shreg[0]),
-                                tx_shreg.eq(Cat(tx_shreg[1:8], C(0,1))),
+                                tx_shreg.eq(Cat(tx_shreg[1:], C(0,1))),
                             ]
                         with m.Else():
                             if self.parity == "none":