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base repository: azonenberg/starshipraider
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compare: 77b05d046875
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  • 1 commit
  • 5 files changed
  • 1 contributor

Commits on Dec 23, 2020

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4 changes: 3 additions & 1 deletion boards/probes/akl-pt2/.gitignore
Original file line number Diff line number Diff line change
@@ -1,4 +1,6 @@
*-cache.lib
output
output/*.gbr
output/*.drl
output/*.zip
*.bak
*-bak
58 changes: 52 additions & 6 deletions boards/probes/akl-pt2/akl-pt2.kicad_pcb
Original file line number Diff line number Diff line change
@@ -2,7 +2,7 @@

(general
(thickness 0.23)
(drawings 15)
(drawings 25)
(tracks 583)
(zones 0)
(modules 6)
@@ -20,6 +20,8 @@
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
@@ -57,7 +59,7 @@
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x030f8_ffffffff)
(layerselection 0x03cf8_ffffffff)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
@@ -221,6 +223,20 @@
)
)

(gr_text "Polyimide stiffener\n0.2mm thick" (at 233.7 47) (layer Eco2.User)
(effects (font (size 1 1) (thickness 0.05)))
)
(gr_line (start 235.9 48.8) (end 230.5 48.8) (layer Eco2.User) (width 0.05) (tstamp 5FE2ECD3))
(gr_line (start 235.9 51.7) (end 235.9 48.8) (layer Eco2.User) (width 0.05))
(gr_line (start 230.5 51.7) (end 235.9 51.7) (layer Eco2.User) (width 0.05))
(gr_line (start 230.5 48.8) (end 230.5 51.7) (layer Eco2.User) (width 0.05))
(gr_text "FR4 stiffener 1.4 mm nominal\nTotal thickness of stiffener and\nPCB not to exceed 1.6 mm" (at 91.5 44.1) (layer Eco1.User)
(effects (font (size 0.75 0.75) (thickness 0.05)))
)
(gr_line (start 94 46.5) (end 86.5 46.5) (layer Eco1.User) (width 0.05))
(gr_line (start 94 54) (end 94 46.5) (layer Eco1.User) (width 0.05))
(gr_line (start 86.5 54) (end 94 54) (layer Eco1.User) (width 0.05))
(gr_line (start 86.5 46.5) (end 86.5 54) (layer Eco1.User) (width 0.05))
(gr_arc (start 94.75 54) (end 94.75 54.25) (angle -90) (layer Edge.Cuts) (width 0.05) (tstamp 5A20B51A))
(gr_arc (start 94.75 46.5) (end 95 46.5) (angle -90) (layer Edge.Cuts) (width 0.05) (tstamp 5A20B514))
(gr_arc (start 95.25 52) (end 95.25 51.75) (angle -90) (layer Edge.Cuts) (width 0.05) (tstamp 5A20B504))
@@ -230,7 +246,7 @@
(gr_line (start 237 49) (end 237 51.5) (layer Edge.Cuts) (width 0.05))
(gr_arc (start 236.75 49) (end 237 49) (angle -90) (layer Edge.Cuts) (width 0.05))
(gr_line (start 95.25 48.75) (end 236.75 48.75) (layer Edge.Cuts) (width 0.05))
(gr_text "AKL-PT2 / A. Zonenberg / Antikernel Labs / Symbiotic EDA / v0.4 / 2020-11-26" (at 127 50.25) (layer B.SilkS) (tstamp 592A4BCD)
(gr_text "AKL-PT2 / A. Zonenberg / Antikernel Labs / Symbiotic EDA / v0.5 / 2020-12-22" (at 127 50.25) (layer B.SilkS) (tstamp 592A4BCD)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_line (start 95 54) (end 95 52) (layer Edge.Cuts) (width 0.05))
@@ -823,7 +839,7 @@
(via (at 236.95 49.75) (size 0.55) (drill 0.25) (layers F.Cu B.Cu) (net 3))
(segment (start 236.45 49.75) (end 237 49.75) (width 0.125) (layer F.Cu) (net 3))

(zone (net 1) (net_name /GND) (layer B.Cu) (tstamp 5F7A9A2A) (hatch edge 0.508)
(zone (net 1) (net_name /GND) (layer B.Cu) (tstamp 5FE2EDA3) (hatch edge 0.508)
(connect_pads (clearance 0.1))
(min_thickness 0.1)
(fill yes (arc_segments 32) (thermal_gap 0.1) (thermal_bridge_width 0.125))
@@ -850,7 +866,7 @@
)
)
)
(zone (net 1) (net_name /GND) (layer F.Cu) (tstamp 5F7A9A27) (hatch edge 0.508)
(zone (net 1) (net_name /GND) (layer F.Cu) (tstamp 5FE2EDA0) (hatch edge 0.508)
(connect_pads yes (clearance 0.225))
(min_thickness 0.1)
(fill yes (arc_segments 32) (thermal_gap 0.1) (thermal_bridge_width 0.125))
@@ -885,7 +901,7 @@
)
)
)
(zone (net 0) (net_name "") (layer F.Mask) (tstamp 0) (hatch edge 0.508)
(zone (net 0) (net_name "") (layer F.Mask) (tstamp 5FE2ED9D) (hatch edge 0.508)
(connect_pads yes (clearance 0.225))
(min_thickness 0.1)
(fill yes (arc_segments 32) (thermal_gap 0.1) (thermal_bridge_width 0.125))
@@ -900,4 +916,34 @@
)
)
)
(zone (net 0) (net_name "") (layer F.Mask) (tstamp 5FE2ED9A) (hatch edge 0.508)
(connect_pads (clearance 0.225))
(min_thickness 0.254)
(fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 235.9 49.3) (xy 235.9 51.2) (xy 237 51.2) (xy 237 49.3)
)
)
(filled_polygon
(pts
(xy 236.873 51.073) (xy 236.027 51.073) (xy 236.027 49.427) (xy 236.873 49.427)
)
)
)
(zone (net 0) (net_name "") (layer B.Mask) (tstamp 5FE2ED97) (hatch edge 0.508)
(connect_pads (clearance 0.225))
(min_thickness 0.254)
(fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 236.6 49.3) (xy 236.6 51.2) (xy 237 51.2) (xy 237 49.3)
)
)
(filled_polygon
(pts
(xy 236.873 51.073) (xy 236.727 51.073) (xy 236.727 49.427) (xy 236.873 49.427)
)
)
)
)
8 changes: 4 additions & 4 deletions boards/probes/akl-pt2/akl-pt2.pro
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
update=Sun 04 Oct 2020 08:53:09 PM PDT
update=Tue 22 Dec 2020 11:03:19 PM PST
version=1
last_client=kicad
[cvpcb]
@@ -49,7 +49,7 @@ CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersLineWidth=0.05
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
@@ -208,9 +208,9 @@ Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=0
[pcbnew/Layer.Eco1.User]
Enabled=0
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=0
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
54 changes: 54 additions & 0 deletions boards/probes/akl-pt2/output/akl-pt2.gvp
Original file line number Diff line number Diff line change
@@ -0,0 +1,54 @@
(gerbv-file-version! "2.0A")
(define-layer! 9 (cons 'filename "akl-pt2-PolyimideStiffener.gbr")
(cons 'visible #t)
(cons 'color #(0 65535 63971))
(cons 'alpha #(65535))
)
(define-layer! 8 (cons 'filename "akl-pt2-B_Cu.gbr")
(cons 'visible #f)
(cons 'color #(65535 32639 29555))
)
(define-layer! 7 (cons 'filename "akl-pt2-B_Mask.gbr")
(cons 'inverted #t)
(cons 'visible #f)
(cons 'color #(49601 0 57568))
)
(define-layer! 6 (cons 'filename "akl-pt2-B_SilkS.gbr")
(cons 'visible #f)
(cons 'color #(30069 62194 26471))
)
(define-layer! 5 (cons 'filename "akl-pt2-F_Paste.gbr")
(cons 'visible #f)
(cons 'color #(65535 50629 13107))
)
(define-layer! 4 (cons 'filename "akl-pt2-F_Cu.gbr")
(cons 'visible #t)
(cons 'color #(54741 65021 13107))
)
(define-layer! 3 (cons 'filename "akl-pt2-F_Mask.gbr")
(cons 'inverted #t)
(cons 'visible #f)
(cons 'color #(53713 6939 26728))
)
(define-layer! 2 (cons 'filename "akl-pt2-Edge_Cuts.gbr")
(cons 'visible #t)
(cons 'color #(0 50115 50115))
)
(define-layer! 1 (cons 'filename "akl-pt2-FR4Stiffener.gbr")
(cons 'visible #t)
(cons 'color #(65535 0 0))
)
(define-layer! 0 (cons 'filename "akl-pt2.drl")
(cons 'visible #t)
(cons 'color #(29555 29555 57054))
(cons 'attribs (list
(list 'autodetect 'Boolean 1)
(list 'zero_suppression 'Enum 0)
(list 'units 'Enum 1)
(list 'digits 'Integer 4)
))
)
(define-layer! -1 (cons 'filename "/nfs4/home/azonenberg/code/starshipraider/boards/probes/akl-pt2/output")
(cons 'color #(0 0 0))
)
(set-render-type! 3)
39 changes: 39 additions & 0 deletions boards/probes/akl-pt2/output/fab-notes.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,39 @@
Part number: akl-pt2 v0.5

General fabrication notes

* Boards to be panelized, 10 boards per panel.
Left side connector will be hand soldered after depanelization.
* Pad finish is ENIG.
* Finished board thickness at left side connector area, including FR4 stiffener, not to exceed 1.6 mm.
* Polyimide stiffener must not overlap contacts at right side of board
* If possible, place UL marking and date code on bottom side of board next to "AKL-PT2" text.
* White silkscreen on bottom side of board only

Impedances

Control to within 10%.

Top side coplanar waveguide (ref to ground on both top and bottom layers).
200 μm trace / 225 μm space = 50 ohm

Suggested stackup
Shengyi SF202C coverlay
1 35 μm (1 oz) RA copper Signal with ground fill
100 μm Panasonic Felios R-F775
2 35 μm (1 oz) RA copper Ground
Shengyi SF202C coverlay
Stiffeners

File naming
akl-pt2-Edge_Cuts.gbr Board outline
akl-pt2.drl Through-board plated holes
akl-pt2-F.Fab.gbr Shows requested location of date code and UL marking
akl-pt2-F_Mask.gbr Top coverlay
akl-pt2-F_Paste.gbr Top solder paste
akl-pt2-F_Cu.gbr Top copper
akl-pt2-B_Cu.gbr Layer 2 copper
akl-pt2-B_Mask.gbr Back coverlay
akl-pt2-B_SilkS.gbr Back silkscreen
akl-pt2-FR4Stiffener.gbr 1.4 mm FR4 stiffener
akl-pt2-PolyimideStiffener.gbr 0.2 mm polyimide stiffener