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#572: add option to suppress generated source line comments #573

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hansfbaier
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Hi I implemented the feature.
Since for verilog the functionality was already there,
I did a regex replace on the other two.

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codecov bot commented Jan 6, 2021

Codecov Report

Merging #573 (54c4f0f) into master (b466b72) will decrease coverage by 0.07%.
The diff coverage is n/a.

Impacted file tree graph

@@            Coverage Diff             @@
##           master     #573      +/-   ##
==========================================
- Coverage   81.50%   81.42%   -0.08%     
==========================================
  Files          49       49              
  Lines        6461     6461              
  Branches     1287     1287              
==========================================
- Hits         5266     5261       -5     
- Misses       1008     1009       +1     
- Partials      187      191       +4     
Impacted Files Coverage Δ
nmigen/_toolchain/cxx.py 94.11% <0.00%> (-5.89%) ⬇️
nmigen/tracer.py 89.18% <0.00%> (-5.41%) ⬇️
nmigen/hdl/ir.py 95.22% <0.00%> (-0.26%) ⬇️
nmigen/build/run.py 22.05% <0.00%> (ø)

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@whitequark
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Using a regex for this purpose is completely unacceptable.

@whitequark whitequark closed this Jan 6, 2021
@hansfbaier
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@whitequark can you give me a clue to where the right place would be for IL? I looked into it, but the src comments are all over the place in the code.

@whitequark
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I don't think this is necessary to do for the IL at all.

@hansfbaier
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hansfbaier commented Jan 6, 2021

I got it: in _ModuleBuilder.__enter__. I would like to actually read and understand the IL too betimes, and also there the source line comments really get in the way of readability

@whitequark
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In that case you can use Yosys to remove the comments like it is done in back.verilog.

@hansfbaier
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hansfbaier commented Jan 6, 2021

You mean, run yosys to filter in rtlil.py:convert or external to nmigen? Inferring from your previous comment, I suppose you suggest the latter.

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