GlasgowEmbedded · Jan 6, 2021
diff --git a/firmware/main.c b/firmware/main.c
@@ -794,7 +794,7 @@ void handle_pending_usb_setup() {
 #define armed_alert EX0
 
 void isr_IE0() __interrupt(_INT_IE0) {
-  // INT_IE0 is level triggered, the ~ALERT line is continously pulled low by the ADC
+  // INT_IE0 is level triggered, the ~ALERT line is continuously pulled low by the ADC
   // So disable this irq unil we have fully handled it, otherwise it permanently triggers
   armed_alert = false;
 }

diff --git a/hardware/boards/glasgow/io_banks.sch b/hardware/boards/glasgow/io_banks.sch
@@ -1687,7 +1687,7 @@ Wire Notes Line
 Wire Notes Line
 	750  4950 900  4950
 Text Notes 3850 2200 0    50   ~ 0
-Synchronization input/output accomodates multiple I/O standards: Vil=0.8V, Vih=2.0V.\n * Nominally, ~SYNC~ is open-drain and 3.3V, with weak internal pull-up.\n * Nevertheless, ~SYNC~ can be connected to 5V circuits directly.\n * ~SYNC~ may also be driven as push-pull to increase bandwidth.\n   Care must be taken to avoid contention. Nevertheless, two Glasgows \n   contending on ~SYNC~ will not exceed absolute maximum ratings.\n   A 47 ohm series resistor is recommended for other drivers.
+Synchronization input/output accommodates multiple I/O standards: Vil=0.8V, Vih=2.0V.\n * Nominally, ~SYNC~ is open-drain and 3.3V, with weak internal pull-up.\n * Nevertheless, ~SYNC~ can be connected to 5V circuits directly.\n * ~SYNC~ may also be driven as push-pull to increase bandwidth.\n   Care must be taken to avoid contention. Nevertheless, two Glasgows \n   contending on ~SYNC~ will not exceed absolute maximum ratings.\n   A 47 ohm series resistor is recommended for other drivers.
 Wire Bus Line
 	5500 5800 6950 5800
 Wire Bus Line

diff --git a/software/glasgow/applet/audio/yamaha_opx/__init__.py b/software/glasgow/applet/audio/yamaha_opx/__init__.py
@@ -26,7 +26,7 @@
 # Bitstream format
 # ----------------
 #
-# The Yamaha DAC bitstream fromat is somewhat underdocumented and confusing. The DAC bitstream
+# The Yamaha DAC bitstream format is somewhat underdocumented and confusing. The DAC bitstream
 # has 16 bit dynamic range and uses 13 bit samples in a bespoke floating point format. These 13 bit
 # samples are padded to 16 bits and transmitted over a serial protocol similar to I²S.
 #

diff --git a/software/glasgow/applet/display/__init__.py b/software/glasgow/applet/display/__init__.py
@@ -3,7 +3,7 @@
 sending commands to a device that alters its transmittance and/or reflectance in response.
 
 Although some devices may receive periodic commands that embed 2d arrays of samples, they are
-still classified under the ``display`` taxon, unless that is the only possibe mode of operation,
+still classified under the ``display`` taxon, unless that is the only possible mode of operation,
 in which case the ``video`` taxon is appropriate.
 
 Examples: HD44780 character LCD, SPI raster LCD, SPI LCD with integrated microcontroller that can

diff --git a/software/glasgow/applet/interface/jtag_svf/__init__.py b/software/glasgow/applet/interface/jtag_svf/__init__.py
@@ -177,7 +177,7 @@ class JTAGSVFApplet(JTAGProbeApplet, name="jtag-svf"):
 
     This applet currently does not implement some SVF features:
         * PIOMAP and PIO are not supported;
-        * Explict state path may not be specified for STATE;
+        * Explicit state path may not be specified for STATE;
         * The SCK clock in RUNTEST is not supported.
 
     If any commands requiring these features are encountered, the applet terminates itself.

diff --git a/software/glasgow/applet/internal/selftest/__init__.py b/software/glasgow/applet/internal/selftest/__init__.py
@@ -60,7 +60,7 @@ class SelfTestApplet(GlasgowApplet, name="selftest"):
           (all pins on all I/O connectors must be floating)
         * pins-pull: detects faults in pull resistor circuits
           (all pins on all I/O connectors must be floating)
-        * pins-loop: detect faults anywhere in the I/O ciruits
+        * pins-loop: detect faults anywhere in the I/O circuits
           (pins A0:A7 must be connected to B0:B7)
         * voltage: detect ADC, DAC or LDO faults
           (on all ports, Vsense and Vio pins must be connected)

diff --git a/software/glasgow/applet/memory/prom/__init__.py b/software/glasgow/applet/memory/prom/__init__.py
@@ -82,7 +82,7 @@ def elaborate(self, platform):
                     pads.a_lat_t.o.eq(a_lat)
                 ]
 
-            # "sa" is the sliced|shifted address, refering to the top-most bits
+            # "sa" is the sliced|shifted address, referring to the top-most bits
             sa_input = self.a[len(pads.a_t.o):]
             # This represents a buffer of those high address bits,
             # not to be confused with the latch pin.

diff --git a/software/glasgow/gateware/i2c.py b/software/glasgow/gateware/i2c.py
@@ -65,7 +65,7 @@ class I2CInitiator(Module):
     :type period_cyc: int
     :param clk_stretch:
         If true, SCL will be monitored for devices stretching the clock. Otherwise,
-        only interally generated SCL is considered.
+        only internally generated SCL is considered.
     :type clk_stretch: bool
 
     :attr busy:
@@ -284,7 +284,7 @@ class I2CTarget(Module):
     :attr read:
         Read strobe. Active for one cycle immediately before latching ``data_o``.
     :attr data_o:
-        Data octet to be transmitted to the initiator. Latched immedately after receiving
+        Data octet to be transmitted to the initiator. Latched immediately after receiving
         a read command.
     """
     def __init__(self, pads):