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The clean circuit step in VPR takes too much time #1622

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acomodi opened this issue Jul 28, 2020 · 3 comments
Open

The clean circuit step in VPR takes too much time #1622

acomodi opened this issue Jul 28, 2020 · 3 comments

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@acomodi
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acomodi commented Jul 28, 2020

There probably has been a regression in the cleaning circuit step (unsure at the moment which changes caused the regression, if it was VPR or Yosys).

We need to identify what causes this increased time in cleaning the circuit and solve that.

This is crucial for big designs as it impacts every step of the P&R flow (e.g. baselitex P&R takes ~40 seconds at each pack, place and route step).
@acomodi acomodi changed the title The Clean Circuit step in VPR takes too much time The clean circuit step in VPR takes too much time Jul 28, 2020
@andrewb1999
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@acomodi Has anyone started looking at this issue yet? On some of my large designs I am seeing the clean circuit step taking 100+ seconds, which severely cuts into the overall p&r speedup I am trying to achieve.

@acomodi
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acomodi commented Sep 4, 2020

@andrewb1999 There was a PR by @litghost that resulted in a great speed-up of the cleaning step in VTR upstream: verilog-to-routing/vtr-verilog-to-routing#1477.

We still need to integrate the upstream VTR with the downstream master+wip, so you may want to temporarily cherry-pick those changes until the new master+wip gets in place

@litghost
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@andrewb1999 The clean circuit step improvement is in. Has the fix been good enough?

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@litghost @andrewb1999 @acomodi