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base repository: amaranth-lang/amaranth
base: 90e2a991f066
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head repository: amaranth-lang/amaranth
compare: 6d417568ad68
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Jul 8, 2020

  1. back.pysim: reset timeline as well. 

    This is a bug that was introduced in 94faf49.
    @whitequark
    whitequark committed Jul 8, 2020
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    3c3cfd4 View commit details
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  2. back.pysim: only extract signal names if VCD is requested. 

    This commit also fixes an issue introduced in 2606ee3 that regressed
simulator startup time and bloated VCD files. (It's actually about
10% faster now than *before* the regression was introduced.)
    @whitequark
    whitequark committed Jul 8, 2020
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    6d41756 View commit details
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