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base repository: azonenberg/starshipraider
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  • 1 commit
  • 5 files changed
  • 1 contributor

Commits on Jul 8, 2020

  1. Finished initial implementation of pod FPGA design. No pin constraint…

    …s except for clock and QSPI because PCB layout is still in progress.
    azonenberg committed Jul 8, 2020
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    ca9d353 View commit details
2 changes: 2 additions & 0 deletions rtl/MAXWELL/pod-fpga/pod-fpga.srcs/constrs_1/new/top.xdc
Original file line number Diff line number Diff line change
@@ -73,3 +73,5 @@ set_property IOSTANDARD LVCMOS33 [get_ports mgmt_mosi]
set_property IOSTANDARD LVCMOS33 [get_ports mgmt_sck]
set_property PACKAGE_PIN G11 [get_ports sysclk_p]
set_property PACKAGE_PIN C11 [get_ports flash_cs_n]

create_clock -period 6.400 -name sysclk_p -waveform {0.000 3.200} [get_ports sysclk_p]
97 changes: 97 additions & 0 deletions rtl/MAXWELL/pod-fpga/pod-fpga.srcs/sources_1/new/PowerControl.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,97 @@
`timescale 1ns/1ps
`default_nettype none
/***********************************************************************************************************************
* *
* STARSHIPRAIDER v0.1 *
* *
* Copyright (c) 2020 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/

module PowerControl(
input wire sysclk,

input wire pod_present_n,
output logic pod_power_en = 0
);

//Synchronize presence-detect signal
wire present_n;

ThreeStageSynchronizer #(
.INIT(0),
.IN_REG(0)
) sync_present(
.clk_in(sysclk),
.din(pod_present_n),
.clk_out(sysclk),
.dout(present_n)
);

//Wait about 850ms after mate before applying power
logic[26:0] count = 0;

enum logic[1:0]
{
STATE_OFF,
STATE_TURNING_ON,
STATE_ON
} state = STATE_OFF;

//Main power control state machine
always_ff @(posedge sysclk) begin

case(state)

STATE_OFF: begin

if(!present_n) begin
count <= 1;
state <= STATE_TURNING_ON;
end

end //end STATE_OFF

STATE_TURNING_ON: begin
count <= count + 1;

if(count == 0) begin
pod_power_en <= 1;
state <= STATE_ON;
end

end //end STATE_TURNING_ON

STATE_ON: begin
if(present_n) begin
pod_power_en <= 0;
state <= STATE_OFF;
end
end //end STATE_ON

endcase

end

endmodule
173 changes: 173 additions & 0 deletions rtl/MAXWELL/pod-fpga/pod-fpga.srcs/sources_1/new/UartBlock.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,173 @@
`timescale 1ns/1ps
`default_nettype none
/***********************************************************************************************************************
* *
* STARSHIPRAIDER v0.1 *
* *
* Copyright (c) 2020 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/

/**
@brief The bank of UARTs and associated FIFOs
*/
module UartBlock(

input wire sysclk,

input wire pod_uart_rx,
output wire pod_uart_tx,

input wire tx_fifo_push_en,
input wire[7:0] tx_fifo_push_data,

input wire rx_fifo_rd_en,
output wire[7:0] rx_fifo_rd_data,
output wire[5:0] rx_fifo_rd_size
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The UART

wire uart_rx_en;
wire[7:0] uart_rx_data;
logic uart_tx_en = 0;
wire uart_tx_done;

wire[7:0] tx_fifo_rdata;

wire uart_rx_en;
wire[7:0] uart_rx_data;

UART uart(
.clk(sysclk),
.clkdiv(16'd1356), //115.2 Kbps @ 156.25 MHz

.rx(pod_uart_rx),
.rxactive(),
.rx_data(uart_rx_data),
.rx_en(uart_rx_en),

.tx(pod_uart_tx),
.tx_data(tx_fifo_rdata),
.tx_en(uart_tx_en),
.txactive(),
.tx_done(uart_tx_done)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit side

logic tx_fifo_rd = 0;

SingleClockFifo #(
.WIDTH(8),
.DEPTH(32),
.USE_BLOCK(0),
.OUT_REG(1)
) tx_fifo (
.clk(sysclk),

.wr(tx_fifo_push_en),
.din(tx_fifo_push_data),

.rd(tx_fifo_rd),
.dout(tx_fifo_rdata),

.overflow(),
.underflow(),
.empty(),
.full(),
.rsize(),
.wsize(),
.reset()
);

//UART read state machine
enum logic[1:0]
{
TX_STATE_IDLE = 0,
TX_STATE_POP = 1,
TX_STATE_SENDING = 2

} tx_state = TX_STATE_IDLE;

always_ff @(posedge sysclk) begin

case(tx_state)

TX_STATE_IDLE: begin
tx_fifo_rd <= 1;
tx_state <= TX_STATE_POP;
end //end TX_STATE_IDLE

TX_STATE_POP: begin

//Set valid flag when reading.
//By the time it's set, the fifo read will be done.
if(tx_fifo_rd)
uart_tx_en <= 1;

//Sending this cycle, wait for send to finish
else
tx_state <= TX_STATE_SENDING;

end //end TX_STATE_POP

TX_STATE_SENDING: begin
if(uart_tx_done)
tx_state <= TX_STATE_IDLE;
end //end TX_STATE_SENDING

endcase

end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receive side

SingleClockFifo #(
.WIDTH(8),
.DEPTH(32),
.USE_BLOCK(0),
.OUT_REG(1)
) rx_fifo (
.clk(sysclk),

.wr(uart_rx_en),
.din(uart_rx_data),

.rd(rx_fifo_rd_en),
.dout(rx_fifo_rd_data),

.overflow(),
.underflow(),
.empty(),
.full(),
.rsize(rx_fifo_rd_size),
.wsize(),
.reset()
);

endmodule
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