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base repository: azonenberg/starshipraider
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base: ca9d353017dc
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head repository: azonenberg/starshipraider
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compare: bcbfc473f115
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  • 1 commit
  • 3 files changed
  • 1 contributor

Commits on Jul 8, 2020

  1. Copy the full SHA
    bcbfc47 View commit details
3 changes: 0 additions & 3 deletions rtl/MAXWELL/pod-fpga/pod-fpga.srcs/sources_1/new/UartBlock.sv
Original file line number Diff line number Diff line change
@@ -57,9 +57,6 @@ module UartBlock(

wire[7:0] tx_fifo_rdata;

wire uart_rx_en;
wire[7:0] uart_rx_data;

UART uart(
.clk(sysclk),
.clkdiv(16'd1356), //115.2 Kbps @ 156.25 MHz
9 changes: 5 additions & 4 deletions rtl/MAXWELL/pod-fpga/pod-fpga.srcs/sources_1/new/top.sv
Original file line number Diff line number Diff line change
@@ -169,9 +169,9 @@ module top(
logic[11:0] uart_tx_fifo_push_en = 0;
logic[7:0] uart_tx_fifo_push_data = 0;

logic[7:0] uart_rx_fifo_rd_en = 0;
wire[7:0] uart_rx_fifo_rd_data[7:0];
wire[5:0] uart_rx_fifo_rd_size[7:0];
logic[11:0] uart_rx_fifo_rd_en = 0;
wire[7:0] uart_rx_fifo_rd_data[11:0];
wire[5:0] uart_rx_fifo_rd_size[11:0];

for(genvar g=0; g<12; g++) begin

@@ -191,7 +191,7 @@ module top(
.pod_uart_rx(pod_uart_rx[g]),

.tx_fifo_push_en(uart_tx_fifo_push_en[g]),
.tx_fifo_push_data(uart_tx_fifo_push_data[g]),
.tx_fifo_push_data(uart_tx_fifo_push_data),

.rx_fifo_rd_en(uart_rx_fifo_rd_en[g]),
.rx_fifo_rd_data(uart_rx_fifo_rd_data[g]),
@@ -218,6 +218,7 @@ module top(

//TODO: allow querying write fifo capacity
//TODO: allow querying/forcing channel power state
//TODO: flash programming
} opcode_t;

enum logic[3:0]
3 changes: 1 addition & 2 deletions rtl/MAXWELL/pod-fpga/pod-fpga.xpr
Original file line number Diff line number Diff line change
@@ -232,7 +232,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7s6ftgb196-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7s6ftgb196-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
@@ -247,7 +247,6 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>