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base repository: azonenberg/starshipraider
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compare: be2723aae933
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  • 1 commit
  • 4 files changed
  • 1 contributor

Commits on Jul 8, 2020

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    be2723a View commit details
4 changes: 4 additions & 0 deletions rtl/MAXWELL/pod-fpga/.gitignore
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*.cache
*.hw
*.ip_user_files
*.runs
75 changes: 75 additions & 0 deletions rtl/MAXWELL/pod-fpga/pod-fpga.srcs/constrs_1/new/top.xdc
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set_property IOSTANDARD LVCMOS33 [get_ports {flash_dq[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {flash_dq[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {flash_dq[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {flash_dq[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_alert[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_alert[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_alert[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_alert[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_alert[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_alert[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_alert[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_alert[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_alert[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_alert[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_alert[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_alert[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_en[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_en[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_en[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_en[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_en[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_en[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_en[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_en[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_en[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_en[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_en[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_power_en[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_present_n[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_present_n[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_present_n[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_present_n[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_present_n[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_present_n[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_present_n[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_present_n[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_present_n[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_present_n[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_present_n[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_present_n[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_rx[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_rx[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_rx[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_rx[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_rx[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_rx[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_rx[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_rx[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_rx[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_rx[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_rx[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_rx[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_tx[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_tx[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_tx[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_tx[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_tx[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_tx[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_tx[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_tx[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_tx[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_tx[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_tx[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pod_uart_tx[0]}]
set_property PACKAGE_PIN C10 [get_ports {flash_dq[3]}]
set_property PACKAGE_PIN D10 [get_ports {flash_dq[2]}]
set_property PACKAGE_PIN B12 [get_ports {flash_dq[1]}]
set_property PACKAGE_PIN B11 [get_ports {flash_dq[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports flash_cs_n]
set_property IOSTANDARD LVCMOS33 [get_ports mgmt_cs_n]
set_property IOSTANDARD LVCMOS33 [get_ports mgmt_miso]
set_property IOSTANDARD LVCMOS33 [get_ports mgmt_mosi]
set_property IOSTANDARD LVCMOS33 [get_ports mgmt_sck]
set_property PACKAGE_PIN G11 [get_ports sysclk_p]
set_property PACKAGE_PIN C11 [get_ports flash_cs_n]
253 changes: 253 additions & 0 deletions rtl/MAXWELL/pod-fpga/pod-fpga.srcs/sources_1/new/top.sv
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`timescale 1ns/1ps
`default_nettype none
/***********************************************************************************************************************
* *
* STARSHIPRAIDER v0.1 *
* *
* Copyright (c) 2020 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/

/**
@brief Top level module for MAXWELL I/O pod control FPGA
The SPI interface
*/
module top(

//Main system clock (156.25 MHz)
input wire sysclk_p,
input wire sysclk_n,

//Boot flash (SCK uses STARTUPE2 primitive and isn't a top level port)
inout wire[3:0] flash_dq,
output wire flash_cs_n,

//SPI to STM32
input wire mgmt_sck,
input wire mgmt_cs_n,
input wire mgmt_mosi,
output wire mgmt_miso,

//Pod UARTs
input wire[11:0] pod_uart_rx,
output wire[11:0] pod_uart_tx,

//Pod power control
input wire[11:0] pod_present_n,
input wire[11:0] pod_power_alert,
output logic[11:0] pod_power_en = 0
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Startup block (needed to drive CCLK to boot flash)

wire cclk_out;

STARTUPE2 #(
.SIM_CCLK_FREQ(10),
.PROG_USR("FALSE")
) startup(
.CLK(),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b0),
.PACK(),
.PREQ(),
.USRCCLKO(cclk_out),
.USRCCLKTS(1'b0),
.USRDONEO(1'b1),
.USRDONETS(1'b0),
.CFGCLK(),
.CFGMCLK(),
.EOS()
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// System clock buffer

wire sysclk_raw;
DifferentialInputBuffer #(
.WIDTH(1),
.IOSTANDARD("LVDS_25"),
.ODT(1),
.OPTIMIZE("SPEED")
) sysclk_ibuf (
.pad_in_p(sysclk_p),
.pad_in_n(sysclk_n),
.fabric_out(sysclk_raw)
);

wire sysclk;
ClockBuffer #(
.TYPE("GLOBAL"),
.CE("NO")
) sysclk_buf (
.clkin(sysclk_raw),
.ce(1'b1),
.clkout(sysclk)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// SPI interface to STM32

SPIDeviceInterface mcu_spi (
.clk(sysclk),
.spi_cs_n(mgmt_cs_n),
.spi_sck(mgmt_sck),
.spi_mosi(mgmt_mosi),
.spi_miso(mgmt_miso),

.cs_falling(),
.tx_data(8'h0),
.tx_data_valid(1'b1),
.rx_data(),
.rx_data_valid()
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// QSPI interface to boot flash

QuadSPIFlashController #(
.SFDP_ADDRESS_32B(0)
) flash_ctrl(
.clk(sysclk),

.spi_sck(cclk_out),
.spi_dq(flash_dq),
.spi_cs_n(flash_cs_n),

.clkdiv(8), //19.53125 MHz

.cmd_en(1'b0),
.cmd_id(),
.cmd_len(),
.cmd_addr(),
.read_data(),
.read_valid(),
.write_data(),
.write_valid(),
.write_ready(),
.busy(),

.capacity_mbits(),
.sfdp_bad()
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Hotswap power control

for(genvar g=0; g<12; g++) begin

//Synchronize presence-detect signal
wire present_n;

ThreeStageSynchronizer #(
.INIT(0),
.IN_REG(0)
) sync_present(
.clk_in(sysclk),
.din(pod_present_n),
.clk_out(sysclk),
.dout(present_n)
);

//Wait about 850ms after mate before applying power
logic[26:0] count = 0;

enum logic[1:0]
{
STATE_OFF,
STATE_TURNING_ON,
STATE_ON
} state = STATE_OFF;

//Main power control state machine
always_ff @(posedge sysclk) begin

case(state)

STATE_OFF: begin

if(!present_n) begin
count <= 1;
state <= STATE_TURNING_ON;
end

end //end STATE_OFF

STATE_TURNING_ON: begin
count <= count + 1;

if(count == 0) begin
pod_power_en[g] <= 1;
state <= STATE_ON;
end

end //end STATE_TURNING_ON

STATE_ON: begin
if(present_n) begin
pod_power_en[g] <= 0;
state <= STATE_OFF;
end
end //end STATE_ON

endcase

end

end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// UARTs and FIFOs

for(genvar g=0; g<12; g++) begin

wire uart_rx_en;
wire[7:0] uart_rx_data;

//The UART itself
UART uart(
.clk(sysclk),
.clkdiv(16'd1356), //115.2 Kbps @ 156.25 MHz

.rx(pod_uart_rx[g]),
.rxactive(),
.rx_data(),
.rx_en(),

.tx(pod_uart_tx[g]),
.tx_data(),
.tx_en(),
.txactive(),
.tx_done()
);

end

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// SPI interface logic

endmodule
257 changes: 257 additions & 0 deletions rtl/MAXWELL/pod-fpga/pod-fpga.xpr
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@@ -0,0 +1,257 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->

<Project Version="7" Minor="44" Path="/nfs4/home/azonenberg/code/starshipraider/rtl/MAXWELL/pod-fpga/pod-fpga.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="ae4d82b5979b479d89eff3a8b7e45131"/>
<Option Name="Part" Val="xc7s6ftgb196-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../antikernel-ipcores/device_abstraction/ClockBuffer.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../antikernel-ipcores/device_abstraction/DifferentialInputBuffer.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../antikernel-ipcores/memory/qspi_flash/QuadSPIFlashController_opcodes.svh">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../antikernel-ipcores/memory/qspi_flash/QuadSPIFlashController.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../antikernel-ipcores/memory/qspi_flash/SFDPParser.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../antikernel-ipcores/interface/spi/SPIDeviceInterface.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../antikernel-ipcores/interface/spi/SPIHostInterface.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../antikernel-ipcores/clock/crossing/ThreeStageSynchronizer.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../antikernel-ipcores/interface/uart/UART.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/top.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="top"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Define Name="XILINX_7SERIES" Val="1"/>
<Define Name="XILINX_SPARTAN7" Val="1"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/top.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/top.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="top"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="11">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7s6ftgb196-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7s6ftgb196-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design" EnableStepBool="1"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>