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  • 1 commit
  • 19 files changed
  • 1 contributor

Commits on Jul 8, 2020

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2 changes: 1 addition & 1 deletion boards/MAXWELL/maxwell-main/1v-rails.sch
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@ $Descr A3 16535 11693
encoding utf-8
Sheet 4 18
Title "MAXWELL Main Board"
Date "2020-07-07"
Date "2020-07-08"
Rev "0.1"
Comp "Antikernel Labs"
Comment1 "Andrew D. Zonenberg"
2 changes: 1 addition & 1 deletion boards/MAXWELL/maxwell-main/clocking.sch
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@ $Descr A3 16535 11693
encoding utf-8
Sheet 15 18
Title "MAXWELL Main Board"
Date "2020-07-07"
Date "2020-07-08"
Rev "0.1"
Comp "Antikernel Labs"
Comment1 "Andrew D. Zonenberg"
2 changes: 1 addition & 1 deletion boards/MAXWELL/maxwell-main/fpgasupport.sch
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@ $Descr A3 16535 11693
encoding utf-8
Sheet 18 18
Title "MAXWELL Main Board"
Date "2020-07-07"
Date "2020-07-08"
Rev "0.1"
Comp "Antikernel Labs"
Comment1 "Andrew D. Zonenberg"
2 changes: 1 addition & 1 deletion boards/MAXWELL/maxwell-main/higher-rails.sch
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@ $Descr A3 16535 11693
encoding utf-8
Sheet 5 18
Title "MAXWELL Main Board"
Date "2020-07-07"
Date "2020-07-08"
Rev "0.1"
Comp "Antikernel Labs"
Comment1 "Andrew D. Zonenberg"
88 changes: 48 additions & 40 deletions boards/MAXWELL/maxwell-main/inputs.sch
Original file line number Diff line number Diff line change
@@ -5,49 +5,14 @@ $Descr A4 11693 8268
encoding utf-8
Sheet 7 18
Title "MAXWELL Main Board"
Date "2020-07-07"
Date "2020-07-08"
Rev "0.1"
Comp "Antikernel Labs"
Comment1 "Andrew D. Zonenberg"
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 3050 1300 1350 1950
U 5F0BA462
F0 "Pod Power" 50
F1 "podpower.sch" 50
F2 "3V3" I L 3050 1450 50
F3 "12V0" I L 3050 1350 50
F4 "GND" I L 3050 1550 50
F5 "P0_12V0" O L 3050 1750 50
F6 "P0_PRESENT" I L 3050 1850 50
F7 "P1_PRESENT" I L 3050 2050 50
F8 "P2_PRESENT" I L 3050 2250 50
F9 "P3_PRESENT" I L 3050 2450 50
F10 "P4_PRESENT" I L 3050 2650 50
F11 "P5_PRESENT" I L 3050 2850 50
F12 "P6_PRESENT" I R 4400 1850 50
F13 "P7_PRESENT" I R 4400 2050 50
F14 "P8_PRESENT" I R 4400 2250 50
F15 "P9_PRESENT" I R 4400 2450 50
F16 "P10_PRESENT" I R 4400 2650 50
F17 "P11_PRESENT" I R 4400 2850 50
F18 "P1_12V0" O L 3050 1950 50
F19 "P2_12V0" O L 3050 2150 50
F20 "P3_12V0" O L 3050 2350 50
F21 "P4_12V0" O L 3050 2550 50
F22 "P5_12V0" O L 3050 2750 50
F23 "P6_12V0" O R 4400 1750 50
F24 "P7_12V0" O R 4400 1950 50
F25 "P8_12V0" O R 4400 2150 50
F26 "P9_12V0" O R 4400 2350 50
F27 "P10_12V0" O R 4400 2550 50
F28 "P11_12V0" O R 4400 2750 50
F29 "I2C1_SDA" B L 3050 3050 50
F30 "I2C1_SCL" I L 3050 3150 50
$EndSheet
$Comp
L xilinx-azonenberg:XC7Sx-FTGB196 U?
U 3 1 5F293D5C
@@ -191,13 +156,13 @@ Text Label 9100 4050 2 50 ~ 0
P9_UART_TX
Text Label 9100 4150 2 50 ~ 0
P9_UART_RX
Text Label 9100 4250 2 50 ~ 0
Text Label 3050 3650 2 50 ~ 0
P10_UART_TX
Text Label 9100 4350 2 50 ~ 0
Text Label 3050 3750 2 50 ~ 0
P10_UART_RX
Text Label 9100 4450 2 50 ~ 0
Text Label 3050 3350 2 50 ~ 0
P11_UART_TX
Text Label 9100 4550 2 50 ~ 0
Text Label 3050 3450 2 50 ~ 0
P11_UART_RX
Text HLabel 6600 3050 2 50 Input ~ 0
K7_CLK_P
@@ -600,4 +565,47 @@ Text Label 7550 5900 2 50 ~ 0
S7_CLK_P
Text Label 7850 5900 0 50 ~ 0
S7_CLK_N
$Sheet
S 3050 1300 1350 2750
U 5F0BA462
F0 "Pod Power" 50
F1 "podpower.sch" 50
F2 "3V3" I L 3050 1450 50
F3 "12V0" I L 3050 1350 50
F4 "GND" I L 3050 1550 50
F5 "P0_12V0" O L 3050 1750 50
F6 "P0_PRESENT" I L 3050 1850 50
F7 "P1_PRESENT" I L 3050 2050 50
F8 "P2_PRESENT" I L 3050 2250 50
F9 "P3_PRESENT" I L 3050 2450 50
F10 "P4_PRESENT" I L 3050 2650 50
F11 "P5_PRESENT" I L 3050 2850 50
F12 "P6_PRESENT" I R 4400 1850 50
F13 "P7_PRESENT" I R 4400 2050 50
F14 "P8_PRESENT" I R 4400 2250 50
F15 "P9_PRESENT" I R 4400 2450 50
F16 "P10_PRESENT" I R 4400 2650 50
F17 "P11_PRESENT" I R 4400 2850 50
F18 "P1_12V0" O L 3050 1950 50
F19 "P2_12V0" O L 3050 2150 50
F20 "P3_12V0" O L 3050 2350 50
F21 "P4_12V0" O L 3050 2550 50
F22 "P5_12V0" O L 3050 2750 50
F23 "P6_12V0" O R 4400 1750 50
F24 "P7_12V0" O R 4400 1950 50
F25 "P8_12V0" O R 4400 2150 50
F26 "P9_12V0" O R 4400 2350 50
F27 "P10_12V0" O R 4400 2550 50
F28 "P11_12V0" O R 4400 2750 50
F29 "I2C1_SDA" B L 3050 3050 50
F30 "I2C1_SCL" I L 3050 3150 50
F31 "P11_UART_TX" O L 3050 3350 50
F32 "P11_UART_RX" I L 3050 3450 50
F33 "P10_UART_RX" I L 3050 3750 50
F34 "P10_UART_TX" O L 3050 3650 50
$EndSheet
NoConn ~ 9100 4550
NoConn ~ 9100 4450
NoConn ~ 9100 4350
NoConn ~ 9100 4250
$EndSCHEMATC
2 changes: 1 addition & 1 deletion boards/MAXWELL/maxwell-main/intermediate-power.sch
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@ $Descr A4 11693 8268
encoding utf-8
Sheet 3 18
Title "MAXWELL Main Board"
Date "2020-07-07"
Date "2020-07-08"
Rev "0.1"
Comp "Antikernel Labs"
Comment1 "Andrew D. Zonenberg"
4 changes: 2 additions & 2 deletions boards/MAXWELL/maxwell-main/iofpga.sch
Original file line number Diff line number Diff line change
@@ -3,9 +3,9 @@ EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 9 18
Sheet 8 18
Title "MAXWELL Main Board"
Date "2020-07-07"
Date "2020-07-08"
Rev "0.1"
Comp "Antikernel Labs"
Comment1 "Andrew D. Zonenberg"
2 changes: 1 addition & 1 deletion boards/MAXWELL/maxwell-main/leftpods.sch
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@ $Descr A3 16535 11693
encoding utf-8
Sheet 12 18
Title "MAXWELL Main Board"
Date "2020-07-07"
Date "2020-07-08"
Rev "0.1"
Comp "Antikernel Labs"
Comment1 "Andrew D. Zonenberg"
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