Update upstream code · YoWASP/yosys@d46cc4e

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Update upstream code

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github-actions[bot] committed Jul 19, 2020

1 parent ce91dba commit d46cc4e

yosys-src

Submodule yosys-src updated 23 files

+1 −1		backends/cxxrtl/cxxrtl_capi.h
+23 −11		backends/verilog/verilog_backend.cc
+1 −1		frontends/verilog/Makefile.inc
+66 −72		frontends/verilog/verilog_parser.y
+2 −0		kernel/yosys.cc
+1 −3		passes/opt/opt_merge.cc
+12 −26		techlibs/anlogic/cells_map.v
+22 −23		techlibs/anlogic/cells_sim.v
+1 −1		techlibs/anlogic/synth_anlogic.cc
+1 −1		techlibs/efinix/Makefile.inc
+5 −1		techlibs/efinix/cells_sim.v
+0 −119		techlibs/efinix/efinix_gbuf.cc
+3 −0		techlibs/efinix/gbuf_map.v
+2 −1		techlibs/efinix/synth_efinix.cc
+0 −1		techlibs/sf2/Makefile.inc
+129 −12		techlibs/sf2/cells_sim.v
+0 −197		techlibs/sf2/sf2_iobs.cc
+10 −4		techlibs/sf2/synth_sf2.cc
+14 −12		tests/arch/anlogic/latches.ys
+6 −0		tests/various/integer_range_bad_syntax.ys
+6 −0		tests/various/integer_real_bad_syntax.ys
+9 −0		tests/various/logic_param_simple.ys
+28 −0		tests/various/signed.ys

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