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base repository: azonenberg/starshipraider
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compare: 41bda824cb34
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Jul 9, 2020

  1. Pod FPGA: updated pinout constraints for signals which are routed on …

    …PCB, confirmed everything is good from the vivado side
    azonenberg committed Jul 9, 2020
    Copy the full SHA
    41bda82 View commit details
Showing with 39 additions and 1 deletion.
  1. +37 −0 rtl/MAXWELL/pod-fpga/pod-fpga.srcs/constrs_1/new/top.xdc
  2. +2 −1 rtl/MAXWELL/pod-fpga/pod-fpga.xpr
37 changes: 37 additions & 0 deletions rtl/MAXWELL/pod-fpga/pod-fpga.srcs/constrs_1/new/top.xdc
Original file line number Diff line number Diff line change
@@ -75,3 +75,40 @@ set_property PACKAGE_PIN G11 [get_ports sysclk_p]
set_property PACKAGE_PIN C11 [get_ports flash_cs_n]

create_clock -period 6.400 -name sysclk_p -waveform {0.000 3.200} [get_ports sysclk_p]

set_property PACKAGE_PIN B6 [get_ports {pod_power_alert[1]}]
set_property PACKAGE_PIN D3 [get_ports {pod_power_alert[6]}]
set_property PACKAGE_PIN C3 [get_ports {pod_uart_rx[7]}]
set_property PACKAGE_PIN A4 [get_ports {pod_uart_rx[6]}]
set_property PACKAGE_PIN A3 [get_ports {pod_present_n[6]}]
set_property PACKAGE_PIN B3 [get_ports {pod_uart_tx[6]}]
set_property PACKAGE_PIN A2 [get_ports {pod_present_n[7]}]
set_property PACKAGE_PIN B5 [get_ports {pod_power_alert[2]}]
set_property PACKAGE_PIN A5 [get_ports {pod_power_alert[0]}]
set_property PACKAGE_PIN B2 [get_ports {pod_uart_tx[7]}]
set_property PACKAGE_PIN B1 [get_ports {pod_power_en[8]}]
set_property PACKAGE_PIN C5 [get_ports {pod_power_alert[3]}]
set_property PACKAGE_PIN C4 [get_ports {pod_power_alert[4]}]
set_property PACKAGE_PIN E4 [get_ports {pod_uart_tx[8]}]
set_property PACKAGE_PIN D4 [get_ports {pod_power_alert[5]}]
set_property PACKAGE_PIN F3 [get_ports {pod_power_en[9]}]
set_property PACKAGE_PIN F2 [get_ports {pod_power_alert[9]}]
set_property PACKAGE_PIN G1 [get_ports {pod_uart_rx[9]}]
set_property PACKAGE_PIN F1 [get_ports {pod_present_n[8]}]
set_property PACKAGE_PIN E2 [get_ports {pod_power_alert[8]}]
set_property PACKAGE_PIN D2 [get_ports {pod_power_alert[7]}]
set_property PACKAGE_PIN D1 [get_ports {pod_uart_rx[8]}]
set_property PACKAGE_PIN C1 [get_ports {pod_power_en[7]}]
set_property PACKAGE_PIN G4 [get_ports {pod_power_alert[10]}]
set_property PACKAGE_PIN F4 [get_ports {pod_power_alert[11]}]
set_property PACKAGE_PIN H4 [get_ports {pod_power_en[11]}]
set_property PACKAGE_PIN H3 [get_ports {pod_power_en[10]}]
set_property PACKAGE_PIN H2 [get_ports {pod_uart_tx[9]}]
set_property PACKAGE_PIN H1 [get_ports {pod_uart_rx[10]}]
set_property PACKAGE_PIN J2 [get_ports {pod_present_n[9]}]
set_property PACKAGE_PIN J1 [get_ports {pod_uart_rx[11]}]
set_property PACKAGE_PIN K4 [get_ports {pod_uart_tx[11]}]
set_property PACKAGE_PIN K3 [get_ports {pod_present_n[11]}]
set_property PACKAGE_PIN J4 [get_ports {pod_uart_tx[10]}]
set_property PACKAGE_PIN J3 [get_ports {pod_present_n[10]}]
set_property PACKAGE_PIN L3 [get_ports {pod_power_en[6]}]
3 changes: 2 additions & 1 deletion rtl/MAXWELL/pod-fpga/pod-fpga.xpr
Original file line number Diff line number Diff line change
@@ -232,7 +232,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7s6ftgb196-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7s6ftgb196-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
@@ -247,6 +247,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>