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XIPHY clock routing bits missing #23

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daveshah1 opened this issue Jul 22, 2020 · 0 comments
Open

XIPHY clock routing bits missing #23

daveshah1 opened this issue Jul 22, 2020 · 0 comments

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@daveshah1
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daveshah1 commented Jul 22, 2020 •
edited

The data for RCLK_XIPHY_OUTER_RIGHT is missing the bits for the pips that select the clocks going out to the XIPHYs:

Screenshot from 2020-07-22 14-46-39

This isn't a massive blocker at the moment as the CMT should probably be a bigger priority, but just making sure this isn't forgotten.
tmichalak pushed a commit to tmichalak/prjuray that referenced this issue Aug 25, 2020
@litghost
Merge pull request f4pga#23 from litghost/update_001
79c2041 
Update 000 to match initial uray DB.
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