from nmigen import *
from nmigen.back.pysim import *

m = Module()
m.domains += ClockDomain('sync_neg', clk_edge='neg')
m.d.comb += ClockSignal('sync_neg').eq(ClockSignal('sync'))

a = Signal()
b = Signal()
m.d.sync += a.eq(1)
m.d.sync_neg += b.eq(1)

sim = Simulator(m)
sim.add_clock(1e-6, domain='sync')

def process():
    yield Tick('sync_neg') # <- ok
    yield Tick('sync') # <- ok
    yield Tick('sync') # <- wrong

sim.add_sync_process(process)
with sim.write_vcd("test.vcd", "test.gtkw", traces=[]):
    sim.run()