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Take a module with a positive and a negative sensitive clock edge and excite it with pysim. When changing from Tick('sync_neg') to Tick('sync') the expected half cycle is added, but after a consecutive Tick('sync') the simulator also only runs another half cycle instead of a full one.
This behaviour can be observed since 2efeb05.
An example reproducing the mentioned issue:
Take a module with a positive and a negative sensitive clock edge and excite it with pysim. When changing from
Tick('sync_neg')
toTick('sync')
the expected half cycle is added, but after a consecutiveTick('sync')
the simulator also only runs another half cycle instead of a full one.This behaviour can be observed since 2efeb05.
An example reproducing the mentioned issue:
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