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base repository: amaranth-lang/amaranth
base: 1f8ba749fbbd
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head repository: amaranth-lang/amaranth
compare: 060ad2584edc
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  • 13 commits
  • 11 files changed
  • 1 contributor

Commits on Jul 16, 2020

  1. CI: use WASM yosys instead of building our own. 

    Fixes #434.
    @whitequark
    whitequark committed Jul 16, 2020
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Commits on Jul 21, 2020

  1. compat.fhdl.bitcontainer: fix value_bits_sign(). 

    This function was broken in commit 659b0e8; some downstream code
expects bits_sign to be e.g. indexable.
    @whitequark
    whitequark committed Jul 21, 2020
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Commits on Jul 22, 2020

  1. CI: replace Travis with GitHub Actions. 

    Fixes #445.
    @whitequark
    whitequark committed Jul 22, 2020
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  2. sim._pycoro: avoid spurious wakeups. 

    This bug was introduced in commit e435a21.
    @whitequark
    whitequark committed Jul 22, 2020
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  3. back.rtlil: lower maximum accepted wire size. 

    In practice wires of just 100000 bits sometimes have unacceptable
performance with Yosys, so stick to Verilog's minimum limit of 65536
bits.
    @whitequark
    whitequark committed Jul 22, 2020
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  4. _toolchain.cxx: new toolchain.

    @whitequark
    whitequark committed Jul 22, 2020
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  5. wip

    @whitequark
    whitequark committed Jul 22, 2020
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  6. wip

    @whitequark
    whitequark committed Jul 22, 2020
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  7. wip

    @whitequark
    whitequark committed Jul 22, 2020
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  8. wip

    @whitequark
    whitequark committed Jul 22, 2020
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  9. wip

    @whitequark
    whitequark committed Jul 22, 2020
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  10. wip

    @whitequark
    whitequark committed Jul 22, 2020
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  11. wip (#439)

    @whitequark
    whitequark committed Jul 22, 2020
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