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  • 1 commit
  • 7 files changed
  • 1 contributor

Commits on Jul 4, 2020

  1. Began work on STM32F031 timer support

    @azonenberg
    azonenberg committed Jul 4, 2020

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    jtojnar Jan Tojnar
    GPG key ID: 7FAB2A15F7A607A4
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    1c093a0 View commit details
Showing with 230 additions and 46 deletions.
  1. +52 −43 devices/inc/stm32f031.h
  2. +12 −3 devices/link/stm32f031.ld
  3. +4 −0 devices/src/stm32f031.cpp
  4. +19 −0 src/peripheral/RCC.cpp
  5. +1 −0 src/peripheral/RCC.h
  6. +93 −0 src/peripheral/Timer.cpp
  7. +49 −0 src/peripheral/Timer.h
95 changes: 52 additions & 43 deletions devices/inc/stm32f031.h
View file
Original file line number Diff line number Diff line change
@@ -62,13 +62,18 @@ enum rcc_ahb

enum rcc_apb2
{
RCC_APB2_USART1 = 0x4000,
RCC_APB2_SPI1 = 0x1000,
RCC_APB2_TIM1 = 0x0800
RCC_APB2_TIM17 = 0x40000,
RCC_APB2_TIM16 = 0x20000,
RCC_APB2_USART1 = 0x04000,
RCC_APB2_SPI1 = 0x01000,
RCC_APB2_TIM1 = 0x00800
};

enum rcc_apb1
{
RCC_APB1_TIM14 = 0x0100,
RCC_APB1_TIM7 = 0x0020,
RCC_APB1_TIM6 = 0x0010,
RCC_APB1_TIM3 = 0x0002,
RCC_APB1_TIM2 = 0x0001
};
@@ -128,33 +133,6 @@ enum usart_bits

extern volatile usart_t USART1;

typedef struct
{
uint32_t CR1;
uint32_t CR2;
uint32_t SMCR;
uint32_t DIER;
uint32_t SR;
uint32_t EGR;
uint32_t CCMR1;
uint32_t CCMR2;
uint32_t CCER;
uint32_t CNT;
uint32_t PSC;
uint32_t ARR;
uint32_t field_30;
uint32_t CCR1;
uint32_t CCR2;
uint32_t CCR3;
uint32_t CCR4;
uint32_t field_44;
uint32_t DCR;
uint32_t DMAR;
} tim_t;

extern volatile tim_t TIM2;
extern volatile tim_t TIM3;

typedef struct
{
uint32_t CFGR1;
@@ -169,19 +147,19 @@ extern volatile syscfg_t SYSCFG;

typedef struct
{
uint32_t CR1;
uint32_t CR2;
uint32_t SR;
uint8_t DR; //STM32f0x1 datasheet page 807, 28.9.4 says the register is 16-bits wide, and that
//"Unused bits are ignored when writing to the register". This is untrue.
//If you access DR as a 16-bit write, you get *two* bytes of data sent.
uint8_t padding1;
uint16_t padding2;
uint32_t CRCPR;
uint32_t RXCRCR;
uint32_t TXCRCR;
uint32_t I2SCFGR;
uint32_t I2SPR;
uint32_t CR1;
uint32_t CR2;
uint32_t SR;
uint8_t DR; //STM32f0x1 datasheet page 807, 28.9.4 says the register is 16-bits wide, and that
//"Unused bits are ignored when writing to the register". This is untrue.
//If you access DR as a 16-bit write, you get *two* bytes of data sent.
uint8_t padding1;
uint16_t padding2;
uint32_t CRCPR;
uint32_t RXCRCR;
uint32_t TXCRCR;
uint32_t I2SCFGR;
uint32_t I2SPR;
} spi_t;

enum spi_cr1_bits
@@ -198,4 +176,35 @@ enum spi_cr1_bits

extern volatile spi_t SPI1;

typedef struct
{
uint32_t CR1;
uint32_t CR2;
uint32_t SMCR;
uint32_t DIER;
uint32_t SR;
uint32_t EGR;
uint32_t CCMR1;
uint32_t CCMR2;
uint32_t CCER;
uint32_t CNT;
uint32_t PSC;
uint32_t ARR;
uint32_t RCR;
uint32_t CCR1;
uint32_t CCR2;
uint32_t CCR3;
uint32_t CCR4;
uint32_t BDTR;
uint32_t DCR;
uint32_t DMAR;
} tim_t;

extern volatile tim_t TIM1;
extern volatile tim_t TIM2;
extern volatile tim_t TIM3;
extern volatile tim_t TIM14;
extern volatile tim_t TIM16;
extern volatile tim_t TIM17;

#endif
15 changes: 12 additions & 3 deletions devices/link/stm32f031.ld
View file
Original file line number Diff line number Diff line change
@@ -74,6 +74,12 @@ SECTIONS
*(.tim2)
. = ALIGN(1024);
*(.tim3)
. = ALIGN(1024);
. += 6144; /* Reserved */
. = ALIGN(1024);
*(.tim14)
. = ALIGN(1024);
. += 1024; /* Reserved */
} > APB1

.sfr_apb2 :
@@ -85,16 +91,19 @@ SECTIONS
. += 7168; /* Reserved */
. += 1024; /* ADC not yet implemented */
. += 1024; /* Reserved */
. += 1024; /* TIM1 not yet implemented */
. = ALIGN(1024);
*(.tim1)
. = ALIGN(1024);
*(.spi1)
. += 1024; /* Reserved */
. = ALIGN(1024);
*(.usart1)
. = ALIGN(1024);
. += 2048; /* Reserved */
. += 1024; /* TIM16 not implemented */
. += 1024; /* TIM17 not implemented */
. = ALIGN(1024);
*(.tim16)
. = ALIGN(1024);
*(.tim17)
. += 3072; /* Reserved */
. += 1024; /* DBGMCU not implemented */
} > APB2
4 changes: 4 additions & 0 deletions devices/src/stm32f031.cpp
View file
Original file line number Diff line number Diff line change
@@ -43,5 +43,9 @@ volatile syscfg_t SYSCFG __attribute__((section(".syscfg")));

volatile usart_t USART1 __attribute__((section(".usart1")));

volatile tim_t TIM1 __attribute__((section(".tim1")));
volatile tim_t TIM2 __attribute__((section(".tim2")));
volatile tim_t TIM3 __attribute__((section(".tim3")));
volatile tim_t TIM14 __attribute__((section(".tim14")));
volatile tim_t TIM16 __attribute__((section(".tim16")));
volatile tim_t TIM17 __attribute__((section(".tim17")));
19 changes: 19 additions & 0 deletions src/peripheral/RCC.cpp
View file
Original file line number Diff line number Diff line change
@@ -59,6 +59,25 @@ void RCCHelper::Enable(volatile spi_t* spi)
RCC.APB2ENR |= RCC_APB2_SPI1;
}

/**
@brief Enable a timer
*/
void RCCHelper::Enable(volatile tim_t* tim)
{
if(tim == &TIM1)
RCC.APB2ENR |= RCC_APB2_TIM1;
else if(tim == &TIM2)
RCC.APB1ENR |= RCC_APB1_TIM2;
else if(tim == &TIM3)
RCC.APB1ENR |= RCC_APB1_TIM3;
else if(tim == &TIM14)
RCC.APB1ENR |= RCC_APB1_TIM14;
else if(tim == &TIM16)
RCC.APB2ENR |= RCC_APB2_TIM16;
else if(tim == &TIM17)
RCC.APB2ENR |= RCC_APB2_TIM17;
}

#ifdef STM32F0

/**
1 change: 1 addition & 0 deletions src/peripheral/RCC.h
View file
Original file line number Diff line number Diff line change
@@ -45,6 +45,7 @@ class RCCHelper
static void Enable(volatile gpio_t* gpio);
static void Enable(volatile usart_t* uart);
static void Enable(volatile spi_t* spi);
static void Enable(volatile tim_t* tim);

#ifdef STM32F0
static void InitializePLLFromInternalOscillator(
93 changes: 93 additions & 0 deletions src/peripheral/Timer.cpp
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,93 @@
/***********************************************************************************************************************
* *
* STM32-CPP v0.1 *
* *
* Copyright (c) 2020 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/

#include <stm32fxxx.h>
#include <ctype.h>
#include <string.h>
#include <peripheral/RCC.h>
#include <peripheral/Timer.h>

/**
@brief Initialize a timer
@param chan The peripheral to use
@param features Capabilities of the requested timer
*/
Timer::Timer(volatile tim_t* chan, Features features)
: m_chan(chan)
, m_features(features)
{
RCCHelper::Enable(chan);
/*
//8-bit word size
//TODO: make this configurable
lane->CR2 = 7 << 8;
//Turn on the peripheral in master mode.
//To prevent problems, we need to have the internal CS# pulled high.
//TODO: support slave mode
lane->CR1 = SPI_MASTER | SPI_SOFT_CS | SPI_INTERNAL_CS;
lane->CR1 |= SPI_ENABLE;
//Calculate correct init value for baud rate divisor
switch(baudDiv)
{
case 2:
break;
case 4:
lane->CR1 |= 0x8;
break;
case 8:
lane->CR1 |= 0x10;
break;
case 16:
lane->CR1 |= 0x18;
break;
case 32:
lane->CR1 |= 0x20;
break;
case 64:
lane->CR1 |= 0x28;
break;
case 128:
lane->CR1 |= 0x30;
break;
//use max value for invalid divisor
case 256:
default:
lane->CR1 |= 0x38;
break;
}
//Enable bidirectional mode if requested
if(!fullDuplex)
lane->CR1 |= SPI_BIDI_MODE;
*/
}
49 changes: 49 additions & 0 deletions src/peripheral/Timer.h
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,49 @@
/***********************************************************************************************************************
* *
* STM32-CPP v0.1 *
* *
* Copyright (c) 2020 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/

#ifndef timer_h
#define timer_h

class Timer
{
public:

enum Features
{
FEATURE_ADVANCED
};

Timer(volatile tim_t* chan, Features features);

protected:
volatile tim_t* m_chan;
Features m_features;
};

#endif