Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: YoWASP/yosys
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: ce91dbafc6df
Choose a base ref
...
head repository: YoWASP/yosys
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 1ef83eaa0103
Choose a head ref
  • 3 commits
  • 3 files changed
  • 2 contributors

Commits on Jul 19, 2020

  1. Update upstream code

    @github-actions @whitequark
    github-actions[bot] authored and whitequark committed Jul 19, 2020
    Copy the full SHA
    2f7882d View commit details

Commits on Jul 26, 2020

  1. Update upstream code

    @github-actions @whitequark
    github-actions[bot] authored and whitequark committed Jul 26, 2020
    Copy the full SHA
    4da546f View commit details

Commits on Jul 30, 2020

  1. Update wasmtime.

    @whitequark
    whitequark committed Jul 30, 2020
    Copy the full SHA
    1ef83ea View commit details
Showing with 3 additions and 3 deletions.
  1. +1 −1 pypi/setup.py
  2. +1 −1 pypi/yowasp_yosys/__init__.py
  3. +1 −1 yosys-src
2 changes: 1 addition & 1 deletion pypi/setup.py
View file
Original file line number Diff line number Diff line change
@@ -33,7 +33,7 @@ def long_description():
setup_requires=["setuptools_scm", "wheel"],
install_requires=[
"importlib_resources; python_version<'3.9'",
"wasmtime~=0.18.2"
"wasmtime~=0.19.0"
],
packages=["yowasp_yosys"],
package_data={"yowasp_yosys": [
2 changes: 1 addition & 1 deletion pypi/yowasp_yosys/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -36,7 +36,7 @@ def _run_wasm_app(wasm_filename, argv):
linker = wasmtime.Linker(store)
wasi = linker.define_wasi(wasmtime.WasiInstance(store,
"wasi_snapshot_preview1", wasi_cfg))
app = linker.instantiate(wasmtime.Module(store,
app = linker.instantiate(wasmtime.Module(store.engine,
importlib_resources.read_binary(__package__, wasm_filename)))
try:
app.exports["_start"]()
2 changes: 1 addition & 1 deletion yosys-src
Submodule yosys-src updated 79 files
+2 −1 CHANGELOG
+3 −1 Makefile
+1 −1 backends/cxxrtl/cxxrtl_capi.h
+13 −0 backends/smt2/smt2.cc
+2 −2 backends/smt2/smtbmc.py
+19 −5 backends/smt2/smtio.py
+23 −11 backends/verilog/verilog_backend.cc
+1 −1 frontends/verilog/Makefile.inc
+66 −72 frontends/verilog/verilog_parser.y
+4 −4 kernel/celltypes.h
+1 −0 kernel/constids.inc
+440 −0 kernel/ff.h
+146 −0 kernel/ffinit.h
+1,239 −0 kernel/satgen.cc
+13 −1,165 kernel/satgen.h
+2 −0 kernel/yosys.cc
+115 −21 passes/memory/memory_dff.cc
+1 −3 passes/opt/opt_merge.cc
+4 −15 passes/opt/pmux2shiftx.cc
+7 −37 passes/opt/wreduce.cc
+8 −28 passes/proc/proc_dlatch.cc
+11 −53 passes/sat/async2sync.cc
+122 −200 passes/sat/clk2fflogic.cc
+14 −1 passes/sat/qbfsat.cc
+1 −0 passes/sat/qbfsat.h
+6 −25 passes/techmap/abc.cc
+7 −41 passes/techmap/dffinit.cc
+25 −80 passes/techmap/dfflegalize.cc
+10 −39 passes/techmap/shregmap.cc
+10 −41 passes/techmap/techmap.cc
+11 −43 passes/techmap/zinit.cc
+12 −26 techlibs/anlogic/cells_map.v
+22 −23 techlibs/anlogic/cells_sim.v
+1 −1 techlibs/anlogic/synth_anlogic.cc
+1 −1 techlibs/efinix/Makefile.inc
+5 −1 techlibs/efinix/cells_sim.v
+0 −119 techlibs/efinix/efinix_gbuf.cc
+3 −0 techlibs/efinix/gbuf_map.v
+2 −1 techlibs/efinix/synth_efinix.cc
+45 −35 techlibs/intel_alm/common/alm_sim.v
+28 −27 techlibs/intel_alm/common/dff_sim.v
+9 −6 techlibs/intel_alm/common/dsp_sim.v
+9 −4 techlibs/intel_alm/common/mem_sim.v
+0 −1 techlibs/sf2/Makefile.inc
+129 −12 techlibs/sf2/cells_sim.v
+0 −197 techlibs/sf2/sf2_iobs.cc
+10 −4 techlibs/sf2/synth_sf2.cc
+1 −113 techlibs/xilinx/arith_map.v
+0 −23 techlibs/xilinx/cells_sim.v
+1 −14 techlibs/xilinx/synth_xilinx.cc
+14 −12 tests/arch/anlogic/latches.ys
+4 −6 tests/arch/intel_alm/mux.ys
+0 −2 tests/arch/xilinx/pmgen_xilinx_srl.ys
+0 −1 tests/opt/opt_rmdff.ys
+21 −0 tests/sat/dff.ys
+41 −0 tests/techmap/cellname.ys
+4 −4 tests/techmap/dfflegalize_adff.ys
+12 −12 tests/techmap/dfflegalize_adff_init.ys
+2 −2 tests/techmap/dfflegalize_adlatch.ys
+6 −6 tests/techmap/dfflegalize_adlatch_init.ys
+9 −9 tests/techmap/dfflegalize_dff.ys
+28 −28 tests/techmap/dfflegalize_dff_init.ys
+4 −4 tests/techmap/dfflegalize_dffsr.ys
+12 −12 tests/techmap/dfflegalize_dffsr_init.ys
+3 −3 tests/techmap/dfflegalize_dlatch.ys
+4 −4 tests/techmap/dfflegalize_dlatch_const.ys
+8 −8 tests/techmap/dfflegalize_dlatch_init.ys
+2 −2 tests/techmap/dfflegalize_dlatchsr.ys
+6 −6 tests/techmap/dfflegalize_dlatchsr_init.ys
+3 −3 tests/techmap/dfflegalize_inv.ys
+1 −1 tests/techmap/dfflegalize_mince.ys
+1 −1 tests/techmap/dfflegalize_minsrst.ys
+6 −6 tests/techmap/dfflegalize_sr.ys
+12 −12 tests/techmap/dfflegalize_sr_init.ys
+2 −2 tests/techmap/zinit.ys
+6 −0 tests/various/integer_range_bad_syntax.ys
+6 −0 tests/various/integer_real_bad_syntax.ys
+9 −0 tests/various/logic_param_simple.ys
+28 −0 tests/various/signed.ys