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base repository: amaranth-lang/amaranth
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compare: 07dc1631054c
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  • 1 commit
  • 1 file changed
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Commits on Jul 30, 2020

  1. hdl.mem: cast reset value for transparent read ports to integer.

    @adamgreig
    adamgreig authored Jul 30, 2020

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    07dc163 View commit details
Showing with 1 addition and 1 deletion.
  1. +1 −1 nmigen/hdl/mem.py
2 changes: 1 addition & 1 deletion nmigen/hdl/mem.py
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Original file line number Diff line number Diff line change
@@ -145,7 +145,7 @@ def elaborate(self, platform):
# value of the data output is forcibly set to the 0th initial value, if any--note that
# many FPGAs do not guarantee this behavior!
if len(self.memory.init) > 0:
self.data.reset = self.memory.init[0]
self.data.reset = operator.index(self.memory.init[0])
latch_addr = Signal.like(self.addr)
f.add_statements(
latch_addr.eq(self.addr),