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compare: 8972afe441e1
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  • 1 commit
  • 5 files changed
  • 1 contributor

Commits on Jul 19, 2020

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    8972afe View commit details
38 changes: 13 additions & 25 deletions rtl/MAXWELL/main-fpga/TriggerSystem_sim_behav.wcfg
Original file line number Diff line number Diff line change
@@ -14,14 +14,14 @@
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="13843636fs"></ZoomEndTime>
<Cursor1Time time="4600800fs"></Cursor1Time>
<ZoomEndTime time="16029604fs"></ZoomEndTime>
<Cursor1Time time="10000000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="272"></NameColumnWidth>
<ValueColumnWidth column_width="79"></ValueColumnWidth>
<ValueColumnWidth column_width="71"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="19" />
<WVObjectSize size="16" />
<wvobject type="logic" fp_name="/TriggerSystem_sim/k7_clk">
<obj_property name="ElementShortName">k7_clk</obj_property>
<obj_property name="ObjectShortName">k7_clk</obj_property>
@@ -72,28 +72,16 @@
</wvobject>
<wvobject fp_name="divider63" type="divider">
</wvobject>
<wvobject type="array" fp_name="/TriggerSystem_sim/xbar_out">
<obj_property name="ElementShortName">xbar_out[2:0][3:0]</obj_property>
<obj_property name="ObjectShortName">xbar_out[2:0][3:0]</obj_property>
<wvobject type="array" fp_name="/TriggerSystem_sim/samples">
<obj_property name="ElementShortName">samples</obj_property>
<obj_property name="ObjectShortName">samples</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TriggerSystem_sim/clock_edges">
<obj_property name="ElementShortName">clock_edges[3:0]</obj_property>
<obj_property name="ObjectShortName">clock_edges[3:0]</obj_property>
<wvobject type="array" fp_name="/TriggerSystem_sim/pconfig">
<obj_property name="ElementShortName">pconfig</obj_property>
<obj_property name="ObjectShortName">pconfig</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TriggerSystem_sim/cs_edges">
<obj_property name="ElementShortName">cs_edges[3:0]</obj_property>
<obj_property name="ObjectShortName">cs_edges[3:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TriggerSystem_sim/data_pipe">
<obj_property name="ElementShortName">data_pipe[3:0]</obj_property>
<obj_property name="ObjectShortName">data_pipe[3:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TriggerSystem_sim/sampled">
<obj_property name="ElementShortName">sampled[7:0]</obj_property>
<obj_property name="ObjectShortName">sampled[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/TriggerSystem_sim/sampled_valid">
<obj_property name="ElementShortName">sampled_valid</obj_property>
<obj_property name="ObjectShortName">sampled_valid</obj_property>
<wvobject type="array" fp_name="/TriggerSystem_sim/match_found">
<obj_property name="ElementShortName">match_found[3:0][3:0]</obj_property>
<obj_property name="ObjectShortName">match_found[3:0][3:0]</obj_property>
</wvobject>
</wave_config>
108 changes: 22 additions & 86 deletions rtl/MAXWELL/main-fpga/main-fpga.srcs/sim_1/new/TriggerSystem_sim.sv
Original file line number Diff line number Diff line change
@@ -209,93 +209,29 @@ module TriggerSystem_sim();
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Trigger logic

lssample_t[2:0] xbar_out;

//Select clock/data/CS signals
InputCrossbar #(
.OUTPUT_COUNT(3)
) xbar (
.clk(clk_312mhz),
.din(samples),
.selects({7'h2, 7'h1, 7'h0}),
.dout(xbar_out)
);

//Find rising clock edges
lssample_t clock_edges;
EdgeDetector clock_edge_detector(
.clk(clk_312mhz),
.look_for_rising(1),
.look_for_falling(0),
.data(xbar_out[1]),
.edges(clock_edges)
);

//Find falling CS# edges
lssample_t cs_edges;
EdgeDetector cs_edge_detector(
.clk(clk_312mhz),
.look_for_rising(0),
.look_for_falling(1),
.data(xbar_out[0]),
.edges(cs_edges)
);

//Pipeline the data to phase align it to the edge detector output
lssample_t data_pipe;
PipelineStage #(.WIDTH(1)) pipe_data (
.clk(clk_312mhz),
.din(xbar_out[2]),
.dout(data_pipe)
);

//Look for edges
wire[7:0] sampled;
lssample_t sampled_valid;

SerialCapture #(
.SERDES_RATE(8)
) serdes (
.clk(clk_312mhz),
.data(data_pipe),
.clock_edges(clock_edges),
.reset_edges(cs_edges),
.sampled(sampled),
.sampled_valid(sampled_valid)
);

//Look for matches
lssample_t found_03;
DigitalComparator #(
.WIDTH(8)
) match_a (
.clk(clk_312mhz),
.din_valid(sampled_valid),
.din_a(sampled),
.din_b(8'h03),
.dout_match(found_03)
);

lssample_t found_12;
DigitalComparator #(
.WIDTH(8)
) match_b (
.clk(clk_312mhz),
.din_valid(sampled_valid),
.din_a(sampled),
.din_b(8'h12),
.dout_match(found_12)
);

lssample_t found_34;
DigitalComparator #(
.WIDTH(8)
) match_c (
`include "SerialPatternMatcher.svh"

//Trigger pconfiguration
spmeconfig_t pconfig;
assign pconfig.muxsel_clk = 1;
assign pconfig.muxsel_rst = 0;
assign pconfig.muxsel_data = 2;
assign pconfig.clock_match_rising = 1;
assign pconfig.clock_match_falling = 0;
assign pconfig.reset_match_rising = 0;
assign pconfig.reset_match_falling = 1;
assign pconfig.targets[0] = 32'h03;
assign pconfig.targets[1] = 32'h12;
assign pconfig.targets[2] = 32'h34;
assign pconfig.targets[3] = 32'h56;

lssample_t[3:0] match_found;

SerialPatternMatcher spme(
.clk(clk_312mhz),
.din_valid(sampled_valid),
.din_a(sampled),
.din_b(8'h34),
.dout_match(found_34)
.samples(samples),
.pconfig(pconfig),
.match_found(match_found)
);

endmodule
Original file line number Diff line number Diff line change
@@ -0,0 +1,131 @@
`default_nettype none
`timescale 1ns/1ps
/***********************************************************************************************************************
* *
* STARSHIPRAIDER v0.1 *
* *
* Copyright (c) 2012-2020 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/

`include "InputState.svh"
`include "SerialPatternMatcher.svh"

/**
@file
@author Andrew D. Zonenberg
@brief Serial pattern matching engine
*/
module SerialPatternMatcher #(
parameter WIDTH = 8
)(
input wire clk,

input wire sample_t samples,
input wire spmeconfig_t pconfig,

output lssample_t[3:0] match_found
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Input crossbar (1 cycle latency)

lssample_t[2:0] xbar_out;

InputCrossbar #(
.OUTPUT_COUNT(3)
) xbar (
.clk(clk),
.din(samples),
.selects({pconfig.muxsel_data, pconfig.muxsel_clk, pconfig.muxsel_rst}),
.dout(xbar_out)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Detect clock/reset edges (1 cycle latency)

//Find rising clock edges
lssample_t clock_edges;
EdgeDetector clock_edge_detector(
.clk(clk),
.look_for_rising(pconfig.clock_match_rising),
.look_for_falling(pconfig.clock_match_falling),
.data(xbar_out[1]),
.edges(clock_edges)
);

//Find falling reset edges
lssample_t rst_edges;
EdgeDetector rst_edge_detector(
.clk(clk),
.look_for_rising(pconfig.reset_match_rising),
.look_for_falling(pconfig.reset_match_falling),
.data(xbar_out[0]),
.edges(rst_edges)
);

//Pipeline the data by a cycle to phase align it to the edge detector output
lssample_t data_pipe;
PipelineStage #(.WIDTH(1)) pipe_data (
.clk(clk),
.din(xbar_out[2]),
.dout(data_pipe)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Deserialize the input data (1 cycle latency)

//Look for edges
wire[7:0] sampled;
lssample_t sampled_valid;

SerialCapture #(
.SERDES_RATE(WIDTH)
) serdes (
.clk(clk),
.data(data_pipe),
.clock_edges(clock_edges),
.reset_edges(rst_edges),
.sampled(sampled),
.sampled_valid(sampled_valid)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Match against external constant values

for(genvar i=0; i<4; i++) begin

DigitalComparator #(
.WIDTH(8)
) match_a (
.clk(clk),
.din_valid(sampled_valid),
.din_a(sampled),
.din_b(pconfig.targets[i][WIDTH-1:0]),
.dout_match(match_found[i])
);

end

endmodule
Original file line number Diff line number Diff line change
@@ -0,0 +1,55 @@
/***********************************************************************************************************************
* *
* STARSHIPRAIDER v0.1 *
* *
* Copyright (c) 2012-2020 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/

`ifndef SerialPatternMatcher_svh
`define SerialPatternMatcher_svh

typedef logic[31:0] target_t;

//Configuration for a SPME
typedef struct packed
{
//Config bits: Input selection
chnum_t muxsel_clk;
chnum_t muxsel_rst;
chnum_t muxsel_data;

//Config bits: Clock/reset polarity
logic clock_match_rising;
logic clock_match_falling;
logic reset_match_rising;
logic reset_match_falling;

//Config bits: Constant values to match against
//(only low WIDTH bits are used)
target_t[3:0] targets;

} spmeconfig_t;

`endif
15 changes: 14 additions & 1 deletion rtl/MAXWELL/main-fpga/main-fpga.xpr
Original file line number Diff line number Diff line change
@@ -30,7 +30,7 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="WTXSimLaunchSim" Val="82"/>
<Option Name="WTXSimLaunchSim" Val="86"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -579,6 +579,19 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/SerialPatternMatcher.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/SerialPatternMatcher.svh">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="top"/>