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base repository: azonenberg/starshipraider
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compare: 182ef455ed3e
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  • 1 commit
  • 10 files changed
  • 1 contributor

Commits on Jul 19, 2020

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    182ef45 View commit details
39 changes: 35 additions & 4 deletions rtl/MAXWELL/main-fpga/TriggerSystem_sim_behav.wcfg
Original file line number Diff line number Diff line change
@@ -14,14 +14,14 @@
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="16029604fs"></ZoomEndTime>
<ZoomEndTime time="12995001fs"></ZoomEndTime>
<Cursor1Time time="10000000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="272"></NameColumnWidth>
<ValueColumnWidth column_width="71"></ValueColumnWidth>
<NameColumnWidth column_width="269"></NameColumnWidth>
<ValueColumnWidth column_width="66"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="16" />
<WVObjectSize size="19" />
<wvobject type="logic" fp_name="/TriggerSystem_sim/k7_clk">
<obj_property name="ElementShortName">k7_clk</obj_property>
<obj_property name="ObjectShortName">k7_clk</obj_property>
@@ -84,4 +84,35 @@
<obj_property name="ElementShortName">match_found[3:0][3:0]</obj_property>
<obj_property name="ObjectShortName">match_found[3:0][3:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TriggerSystem_sim/rconfig">
<obj_property name="ElementShortName">rconfig</obj_property>
<obj_property name="ObjectShortName">rconfig</obj_property>
</wvobject>
<wvobject type="array" fp_name="/TriggerSystem_sim/parallel_match_found">
<obj_property name="ElementShortName">parallel_match_found[3:0][3:0]</obj_property>
<obj_property name="ObjectShortName">parallel_match_found[3:0][3:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="array" fp_name="/TriggerSystem_sim/parallel_match_found[3]">
<obj_property name="ElementShortName">[3][3:0]</obj_property>
<obj_property name="ObjectShortName">[3][3:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/TriggerSystem_sim/parallel_match_found[2]">
<obj_property name="ElementShortName">[2][3:0]</obj_property>
<obj_property name="ObjectShortName">[2][3:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/TriggerSystem_sim/parallel_match_found[1]">
<obj_property name="ElementShortName">[1][3:0]</obj_property>
<obj_property name="ObjectShortName">[1][3:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
<wvobject type="array" fp_name="/TriggerSystem_sim/parallel_match_found[0]">
<obj_property name="ElementShortName">[0][3:0]</obj_property>
<obj_property name="ObjectShortName">[0][3:0]</obj_property>
<obj_property name="isExpanded"></obj_property>
</wvobject>
</wvobject>
<wvobject fp_name="divider682" type="divider">
</wvobject>
</wave_config>
Original file line number Diff line number Diff line change
@@ -80,7 +80,7 @@ module TriggerSystem_sim();
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Test signal source
// Test signal source 1 : SPI

wire sck;
wire mosi;
@@ -170,10 +170,22 @@ module TriggerSystem_sim();

wire[91:0] low_speed_raw;

//SPI bus
assign low_speed_raw[0] = cs_n;
assign low_speed_raw[1] = sck;
assign low_speed_raw[2] = mosi;
assign low_speed_raw[91:3] = 0;

//8-bit parallel bus
assign low_speed_raw[3] = tx_data[0];
assign low_speed_raw[4] = tx_data[1];
assign low_speed_raw[5] = tx_data[2];
assign low_speed_raw[6] = tx_data[3];
assign low_speed_raw[7] = tx_data[4];
assign low_speed_raw[8] = tx_data[5];
assign low_speed_raw[9] = tx_data[6];
assign low_speed_raw[10] = tx_data[7];

assign low_speed_raw[91:11] = 0;

wire[91:0] low_speed_p;
wire[91:0] low_speed_n;
@@ -209,7 +221,7 @@ module TriggerSystem_sim();
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Trigger logic

`include "SerialPatternMatcher.svh"
`include "PatternMatcher.svh"

//Trigger pconfiguration
spmeconfig_t pconfig;
@@ -238,4 +250,36 @@ module TriggerSystem_sim();
.match_found(match_found)
);

//Parallel config
ppmeconfig_t rconfig;
assign rconfig.muxsel_clk = 1;
assign rconfig.muxsel_data[0] = 3;
assign rconfig.muxsel_data[1] = 4;
assign rconfig.muxsel_data[2] = 5;
assign rconfig.muxsel_data[3] = 6;
assign rconfig.muxsel_data[4] = 7;
assign rconfig.muxsel_data[5] = 8;
assign rconfig.muxsel_data[6] = 9;
assign rconfig.muxsel_data[7] = 10;
assign rconfig.clock_match_rising = 1;
assign rconfig.clock_match_falling = 0;
assign rconfig.target_values[0] = 32'h03;
assign rconfig.target_values[1] = 32'h12;
assign rconfig.target_values[2] = 32'h34;
assign rconfig.target_values[3] = 32'h56;
assign rconfig.target_masks[0] = 32'hff;
assign rconfig.target_masks[1] = 32'hff;
assign rconfig.target_masks[2] = 32'hff;
assign rconfig.target_masks[3] = 32'hff;

lssample_t[3:0] parallel_match_found;

ParallelPatternMatcher ppme(
.clk(clk_312mhz),
.samples(samples),
.pconfig(rconfig),
.match_found(parallel_match_found)
);


endmodule
Original file line number Diff line number Diff line change
@@ -0,0 +1,82 @@
`default_nettype none
`timescale 1ns/1ps
/***********************************************************************************************************************
* *
* STARSHIPRAIDER v0.1 *
* *
* Copyright (c) 2012-2020 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/

`include "InputState.svh"

/**
@file
@author Andrew D. Zonenberg
@brief Compares two inputs together, applying a bitmask to the first.
Each serial bit is tested for a match separately.
*/
module DigitalMultiComparator #(
parameter WIDTH = 1
) (
input wire clk,

input wire lssample_t din_valid,
input lssample_t[WIDTH-1:0] din_a,
input wire[WIDTH-1:0] mask_a,
input wire[WIDTH-1:0] din_b,

output lssample_t dout_match = 0
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Matching logic

always_ff @(posedge clk) begin

dout_match <= 0;

for(integer i=0; i<4; i++) begin

//Only check if input clock edge is valid
if(din_valid[i]) begin

//Assume match
dout_match[i] <= 1;

//Check each bit
for(integer j=0; j<WIDTH; j++) begin
if( (din_a[j][i] & mask_a[j]) != din_b[j])
dout_match[i] <= 0;
end

end

end

end

endmodule

Original file line number Diff line number Diff line change
@@ -36,6 +36,12 @@
@author Andrew D. Zonenberg
@brief Crossbar for feeding input data to trigger blocks
Select values:
0...5b Input signals
5c...7d Undefined
7e All 0s
7f All 1s
Latency: 1 clock
*/
module InputCrossbar #(
@@ -55,8 +61,16 @@ module InputCrossbar #(

always_ff @(posedge clk) begin

for(integer i=0; i<OUTPUT_COUNT; i++)
dout[i] <= din.lo[selects[i]];
for(integer i=0; i<OUTPUT_COUNT; i++) begin

if(selects[i] == 7'h7f)
dout[i] <= 4'hf;
else if(selects[i] == 7'h7e)
dout[i] <= 4'h0;
else
dout[i] <= din.lo[selects[i]];

end

end

Original file line number Diff line number Diff line change
@@ -86,12 +86,12 @@ module LowSpeedInputs #(
wire[91:0] probe_in_delay;

//TODO: separate delay values for each pod based on final PCB trace lengths
parameter integer POD_DELAYS[11:0] =
localparam integer POD_DELAYS[11:0] =
{
25,
25,
25,
25,
26,
27,
28,
25,
25,
25,
Original file line number Diff line number Diff line change
@@ -0,0 +1,107 @@
`default_nettype none
`timescale 1ns/1ps
/***********************************************************************************************************************
* *
* STARSHIPRAIDER v0.1 *
* *
* Copyright (c) 2012-2020 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/

`include "InputState.svh"
`include "PatternMatcher.svh"

/**
@file
@author Andrew D. Zonenberg
@brief Parallel pattern matching engine (3 cycle latency)
*/
module ParallelPatternMatcher #(
parameter WIDTH = 8
)(
input wire clk,

input wire sample_t samples,
input wire ppmeconfig_t pconfig,

output lssample_t[3:0] match_found
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Input crossbar (1 cycle latency)

lssample_t[WIDTH:0] xbar_out;

InputCrossbar #(
.OUTPUT_COUNT(WIDTH+1)
) xbar (
.clk(clk),
.din(samples),
.selects({pconfig.muxsel_clk, pconfig.muxsel_data[WIDTH-1:0]}),
.dout(xbar_out)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Pipeline the data and edge detect the clock (1 cycle latency)

//Data pipeline stage
lssample_t[WIDTH-1:0] data_pipe;

PipelineStage #(
.WIDTH(WIDTH)
) pipe (
.clk(clk),
.din(xbar_out[WIDTH-1:0]),
.dout(data_pipe)
);

//Clock edge detection
lssample_t clock_edges;
EdgeDetector clock_edge_detector(
.clk(clk),
.look_for_rising(pconfig.clock_match_rising),
.look_for_falling(pconfig.clock_match_falling),
.data(xbar_out[WIDTH]),
.edges(clock_edges)
);

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Match against external constant values (1 cycle latency)

for(genvar i=0; i<4; i++) begin

DigitalMultiComparator #(
.WIDTH(8)
) match_a (
.clk(clk),
.din_valid(clock_edges),
.din_a(data_pipe),
.mask_a(pconfig.target_masks[i][WIDTH-1:0]),
.din_b(pconfig.target_values[i][WIDTH-1:0]),
.dout_match(match_found[i])
);

end

endmodule
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