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vendor.xilinx_{7series,ultrascale}: add SIM_DEVICE parameter #444

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merged 1 commit into from Jul 23, 2020

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The parameter defaults to "ULTRASCALE", even when synthesizing for 7-series devices. This could lead to a simulation/synthesis mismatch, and causes a warning.

Fixes #438.

The parameter defaults to "ULTRASCALE", even when synthesizing for
7-series devices. This could lead to a simulation/synthesis mismatch,
and causes a warning.

Fixes #438.
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codecov bot commented Jul 22, 2020

Codecov Report

Merging #444 into master will not change coverage.
The diff coverage is n/a.

Impacted file tree graph

@@           Coverage Diff           @@
##           master     #444   +/-   ##
=======================================
  Coverage   81.68%   81.68%           
=======================================
  Files          40       40           
  Lines        6099     6099           
  Branches     1242     1242           
=======================================
  Hits         4982     4982           
- Misses        936      937    +1     
+ Partials      181      180    -1     
Impacted Files Coverage Δ
nmigen/build/run.py 31.25% <0.00%> (ø)

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@whitequark whitequark force-pushed the master branch 2 times, most recently from c86aaa2 to d71e19e Compare July 22, 2020 09:28
@whitequark whitequark merged commit c75fa45 into master Jul 23, 2020
@whitequark whitequark deleted the xilinx-sim_device branch July 23, 2020 16:38
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wrong type of buffer primitive used in series 7
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