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base repository: GlasgowEmbedded/glasgow
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base: 85e158103ebe
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head repository: GlasgowEmbedded/glasgow
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compare: 72cb28b2bd15
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Jul 22, 2020

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    72cb28b View commit details
Showing with 3 additions and 2 deletions.
  1. +3 −2 software/glasgow/gateware/__init__.py
5 changes: 3 additions & 2 deletions software/glasgow/gateware/__init__.py
Original file line number Diff line number Diff line change
@@ -25,9 +25,10 @@ def setup_wrapper():
if isinstance(self.tb, CompatModule):
compat_run_simulation(self.tb, setup_wrapper(), vcd_name="test.vcd")
if isinstance(self.tb, Elaboratable):
with Simulator(self.tb, vcd_file=open("test.vcd", "w")) as sim:
sim = Simulator(self.tb)
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
sim.add_clock(1e-8)
sim.add_sync_process(setup_wrapper())
sim.add_sync_process(setup_wrapper)
sim.run()
return wrapper