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Branch : Quicklogic : Crash while running analysis on the attached design using logic cell macro #1588

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rakeshm75 opened this issue Jul 13, 2020 · 4 comments
Open

Branch : Quicklogic : Crash while running analysis on the attached design using logic cell macro #1588

rakeshm75 opened this issue Jul 13, 2020 · 4 comments
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@mkurc-ant

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@rakeshm75
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Get following error when running the attached design (using logic cell macro):

Writing Implementation Netlist: top_post_synthesis.v
Writing Implementation Netlist: top_post_synthesis.blif
Writing Implementation SDF : top_post_synthesis.sdf
make[3]: *** [quicklogic/pp3/tests/quicklogic_testsuite/test_logic_cell/test_logic_cell-ql-chandalar/ql-s3-ql-eos-s3-virt-ql-eos-s3-wlcsp/analysis.log] Error 134
make[2]: *** [quicklogic/pp3/tests/quicklogic_testsuite/test_logic_cell/CMakeFiles/test_logic_cell-ql-chandalar_analysis.dir/all] Error 2
make[1]: *** [quicklogic/pp3/tests/quicklogic_testsuite/test_logic_cell/CMakeFiles/test_logic_cell-ql-chandalar_analysis.dir/rule] Error 2
make: *** [quicklogic/pp3/tests/quicklogic_testsuite/test_logic_cell/CMakeFiles/test_logic_cell-ql-chandalar_analysis.dir/rule] Error 2

counter_8bit.zip
@rakeshm75
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Added one more test case

test_logic_cell.zip

@mkurc-ant
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Looks like a VPR segfautl. Will check that.

@mkurc-ant mkurc-ant self-assigned this Jul 14, 2020
@mkurc-ant
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I've identified the issue. It appears that i has already been fixed in upstream VPR (as of aa042b61c4). I'll go through the procedure of integration upstream VPR into symbiflow. Once that is done a new conda package with the updated VPR will be uploaded with the issue fixed.

@mkurc-ant mkurc-ant mentioned this issue Jul 16, 2020
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@mkurc-ant
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@rakeshm75 @tpagarani If you cherry pick the following commits from the upstream VTR into your fork then the issue should be solved: 0f1c496 and 197d65a.

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@mkurc-ant @rakeshm75