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write next state to vcd instead of curr state, since state is written just prior to commit #430

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merged 1 commit into from Jul 13, 2020

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programmerjake
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@programmerjake programmerjake commented Jul 13, 2020

Fixes #429

I tested it and it seems to work!
@whitequark You can add a regression test later if you want.

@whitequark
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So actually a better fix would be to accumulate pending throughout every delta cycle and then write things only once per step. Unless you need this fixed urgently I'd rather do that.

@programmerjake
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Would you be willing to merge this fix while you finish off the better fix, since this one is pretty simple? I'm not 100% sure, but I think #429 is blocking several people in Libre-SOC to some extent.

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codecov bot commented Jul 13, 2020

Codecov Report

Merging #430 into master will decrease coverage by 0.00%.
The diff coverage is 100.00%.

Impacted file tree graph

@@            Coverage Diff             @@
##           master     #430      +/-   ##
==========================================
- Coverage   81.72%   81.71%   -0.01%     
==========================================
  Files          40       40              
  Lines        6100     6099       -1     
  Branches     1243     1242       -1     
==========================================
- Hits         4985     4984       -1     
  Misses        935      935              
  Partials      180      180              
Impacted Files Coverage Δ
nmigen/sim/pysim.py 90.62% <100.00%> (-0.04%) ⬇️

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@whitequark whitequark merged commit 58f1d4b into amaranth-lang:master Jul 13, 2020
@programmerjake
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Thanks!

@programmerjake programmerjake deleted the fix-429 branch July 13, 2020 02:24
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values in vcd are zero despite simulation's nonzero values
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