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File "/adhome/lsharma/git_work/quicklogic-corp/symbiflow-arch-defs/quicklogic/common/utils/fasm2bels.py", line 873, in produce_verilog
module.parse_bels()
File "/adhome/lsharma/git_work/quicklogic-corp/symbiflow-arch-defs/quicklogic/common/utils/verilogmodule.py", line 551, in parse_bels
inputs[inputname] = self.cand_map[currloc][wire[1]]
KeyError: 'CAND3'
The text was updated successfully, but these errors were encountered:
For the designs quicklogic/pp3/tests/quicklogic_testsuit/ram_test or fifo_test we get the get error for the target *_bit_v
File "/adhome/lsharma/git_work/quicklogic-corp/symbiflow-arch-defs/quicklogic/common/utils/fasm2bels.py", line 873, in produce_verilog
module.parse_bels()
File "/adhome/lsharma/git_work/quicklogic-corp/symbiflow-arch-defs/quicklogic/common/utils/verilogmodule.py", line 551, in parse_bels
inputs[inputname] = self.cand_map[currloc][wire[1]]
KeyError: 'CAND3'
The text was updated successfully, but these errors were encountered: