New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
PS7 block not initialized on series-7 Zynq targets #441
Comments
Try something like:
|
Did this work for you? |
it did not. |
Right, there's likely a bug in the RTLIL backend that prevents this from working. I'll take a look. |
From IRC:
|
Now that I think again about it, this might be a Yosys bug. |
from a question on the xilinx forums, it seems like putting a dummy with all the wires connected to some values (or disconnected- |
I think the Try adding the attribute m.d.submodules += Instance("PS7", a_DONT_TOUCH="true") I use it with PS8 for ZynqMP and it works. https://github.com/satellogic/nmigen-zynq/blob/89c0c87801f3a6d5f2059b9af88c39231e24d41d/nmigen_zynq/ps.py#L119 |
@andresdemski it is actually omitted by nmigen if it doesn't have any ports, so simply adding a attribute is not enough. See my comment here and the source code snippet linked to in there. |
I'm using Vivado 2019.2, with the artix z7 board. Vivado spits this warning:
this should be simple enough to fix in verilog, but I don't know how to fix that in nMigen.
The text was updated successfully, but these errors were encountered: