Try something like:

m.submodules += Instance("PS7")

Did this work for you?

it did not.

Right, there's likely a bug in the RTLIL backend that prevents this from working. I'll take a look.

From IRC:

[11:45:03] <vup> this seems to be the problematic line: https://github.com/nmigen/nmigen/blob/7aedb3e77045e865ea8e676b4a6616d03599a3ad/nmigen/back/rtlil.py#L858-L859 Considering Instances could be nested arbitrarily deep inside submodules without any ports this doesn't seem correct

@rroohhh Ah right, so the problem that 9faa1d3 was fixing is that Yosys treats empty modules as black boxes by default. Maybe they should contain a dummy wire instead or something.

Now that I think again about it, this might be a Yosys bug.

from a question on the xilinx forums, it seems like putting a dummy with all the wires connected to some values (or disconnected- open in vhdl) should solve the issue. I am not sure this is optimal- this means many many lines of code for this one small problem.

Try something like:

m.d.submodules += Instance("PS7")

I think the PS7 is removed during the synthesis.

Try adding the attribute DONT_TOUCH:

m.d.submodules += Instance("PS7", a_DONT_TOUCH="true")

I use it with PS8 for ZynqMP and it works. https://github.com/satellogic/nmigen-zynq/blob/89c0c87801f3a6d5f2059b9af88c39231e24d41d/nmigen_zynq/ps.py#L119

@andresdemski it is actually omitted by nmigen if it doesn't have any ports, so simply adding a attribute is not enough. See my comment here and the source code snippet linked to in there.