SDC plugin does not output the BUFG out clocks anymore #64
Comments
See issue: chipsalliance/yosys-f4pga-plugins#64 Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
|
@acomodi So the current behavior is expected as the clock parameters (period, waveform) on the BUFGs are the same as on the PLL output wires that are driving them. Of course what is worrying is the fact that the clocks for crg_clkout1 and crg_clkout2 so CLKOUT1 and CLKOUT2 outputs of the PLL are not in the SDC. Is the SDC you pasted complete? |
@tmichalak Those are absent as the test is the minilitex one, wihtout DDR and Ethernet. Yosys prunes away the BUFG related to CLKOUT1 and CLKOUT2, and the SDC plugin discards those nets and does not output them in the final SDC, so that SDC is complete indeed. What is missing though is also the CLKIN to the PLL which I am not sure why was not added. |
|
You mean |
See issue: chipsalliance/yosys-f4pga-plugins#64 Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
|
Poke? |
|
What is the status here? |
|
The main issue comes from the fact that VPR is not able to propagate the clocks. In fact, this is what results when running in VPR: The only constrained nets are the PLL clock output nets. As a longer term solution we might need to add capabilities in VPR to understand that a clock net that, for instance, passes through a BUFG, has the same constraint as the PLL output. |
|
So I believe the fixes in #54 are good, but we do need a "verbose" SDC output for VPR. So make @acomodi / @tmichalak I believe that this would resolve the issue? |
|
@tmichalak - Yes, we most certainly want to be able to write a SDC file with all clocks propagated, that was one of the points of pulling the data into Yosys in the first place... |
With the clock propagation enhancements done in #54, the resulting SDC does not take into account the output clock from BUFGs connected to the PLL outputs.
This causes VPR to not correctly constrain clock signals, resulting in higher run-time and an
nanCPD, such as in the following example:Resulting SDC:
This example is taken from the LiteX mini design, for which the
crg_clkout1andcrg_clkout2clock nets are unconnected, therefore they do not end up in the SDC, and this is expected.The problem though is that the correct SDC for VPR should have also the
crg_clkoutN_bufNclocks as well.I notice also that the clock constraint for the input clock net to the PLL is missing as well.
The text was updated successfully, but these errors were encountered: