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Remove workaround with skipping clocks on dangling wires #59

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tmichalak opened this issue Dec 2, 2020 · 2 comments
Open

Remove workaround with skipping clocks on dangling wires #59

tmichalak opened this issue Dec 2, 2020 · 2 comments

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@tmichalak
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PR #57 has been created to fix the reported problem.
This is needed to the 200T designs to work with SymbiFlow, but the problem is in fact in VPR as it sweeps the netlist and invalidates an SDC that was originally valid.
@tmichalak tmichalak mentioned this issue Dec 2, 2020
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@mithro
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mithro commented Dec 2, 2020

@tmichalak - Didn't we discover that there are two issues;

  • (a) Yosys is producing output in the BLIF that VPR sweeps.
  • (b) VPR is sweeping away stuff but not updating the SDC.

@tmichalak
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@tmichalak - Didn't we discover that there are two issues;

(a) Yosys is producing output in the BLIF that VPR sweeps.
(b) VPR is sweeping away stuff but not updating the SDC.

@mithro Yes, that is correct.

mglb pushed a commit to antmicro/yosys-f4pga-plugins that referenced this issue Apr 3, 2023
@kamilrakoczy
Merge pull request chipsalliance#59 from antmicro/remove-libraries-files
d444cb1 
Remove parse of library files in Surelog
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@mithro @tmichalak