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Fix curly brackets support in get_ports commands #62
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I'm new to pragrammimg. let me handle this issue |
Sure! In case you need any additional information, don't hesitate to ask! |
can you assist me in this |
Of course! Here is the plugin source file: First, make sure that you can compile Yosys and run it with the XDC plugin. Tomorrow, I can give you more detailed information how to do that and test the plugin.
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tell me more on how to do that |
Here are instructions that will allow you to reproduce my error. I created another branch with the failing syntax, so it will be easier for you to set up a working project.
Note that this may take about 1h to generate the FPGA architecture for the chip. Make sure that after changing the XDC plugin in the |
Many public XDC files provide
get_ports
arguments in curly brackets:https://github.com/Digilent/digilent-xdc/blob/master/Arty-A7-35-Master.xdc#L7
Currently, support for this feature is missing / incomplete. The following XDC file:
causes the following error during the Yosys synthesis step:
After removing the curly brackets, everything works as intended:
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