Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Consistently use XDC constraints in all tests #1859

Open
acomodi opened this issue Dec 8, 2020 · 1 comment
Open

Consistently use XDC constraints in all tests #1859

acomodi opened this issue Dec 8, 2020 · 1 comment

Comments

@acomodi
Copy link
Contributor

acomodi commented Dec 8, 2020

Currently, the constraints applied to the various test designs can be of two forms:

  • XDC: This contains both IO placement and clock constraints, and the XDC is parsed by the yosys plugin and generates information on where to constrain IOPADs as well as the SDC file for constraining clock nets in VPR.

  • PCF+SDC: The IO placement constraints and clock constraints are in separate manually written files.

IMO we should be consistent in using one form of constraints only (at least for the xc7 devices), as using both forms is a source of maintainability issues as well as confusion, and the right format should be the XDC.

This issue is to keep track of the effort in moving all the tests' constraints towards the XDC format.

In addition, we should add clock constraints where missing, as there are tests which do not have them (of course only where the clock is being used)
@mithro
Copy link
Contributor

mithro commented Dec 8, 2020 •
edited by unfurl-links bot

Sadly, I for compatibility reasons we will need to support PCF+SDC formats long term (and the older UCF format from ISE too).

However, to isolate the maintenance burden, only one tool should support all these formats and every downstream tool should use the output of the upstream tool. This is the aim with the yosys-symbiflow-plugins -- All the file formats are imported into common Yosys internal data structures and then Yosys can export the data in the format needed by the downstream tools. See this diagram @ https://docs.google.com/drawings/d/1r2LXypJF5AD40LfHegml3_fIvPT2jZ3n2OZYW9-9dLU/edit
Yosys and Constraints System

Google Docs
Yosys Verilog Design .v Timing Constraints .sdc Creates Cells Annotates Cells Optimizer Cells Cells Cells Cells Cells Renamed Cells Netlist .blif Timing Constraints .sdc From Cells From Annotations Optimizer preserves cell annotations but can eliminate cells and mangle net names Annotations can a...

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
2 participants
@mithro @acomodi