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Integrating design with bus. #615

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m-kru opened this issue May 23, 2021 · 4 comments
Open

Integrating design with bus. #615

m-kru opened this issue May 23, 2021 · 4 comments
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@m-kru
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m-kru commented May 23, 2021

I struggle to find an documentation or tutorial on how to integrate a design with the bus (such as AXI or Wishbone), and whether there is an option to automatically generate status and control registers.
I have found in https://github.com/m-labs/misoc README that there used to be some kind of "automatic CSR maps" but it also misses to point to the source.

Is it possible to automatically generate control/status registers with nmigen?
If yes, is there any tutorial on how to do that?
@whitequark
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This is handled as a part of https://github.com/nmigen/nmigen-soc/. However, that repository contains only a partial implementation at the moment.

@m-kru
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m-kru commented May 23, 2021

@whitequark Looks like there has been no work for few months.

@whitequark
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There's been a pandemic.

@ydnatag
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ydnatag commented Jun 5, 2021

How can we contribute to the project?

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