# ** Error: (vsim-3033) Instantiation of 'CARRY4_VPR' failed. The design unit was not found.
#    Time: 0 ps  Iteration: 0  Instance: /tb/dut File: top_post_synthesis.v Line: 1344
#         Searched libraries:
#             /home/vegg/Documents/FPGA/simulation/gate_work
#             /home/vegg/Documents/FPGA/simulation/gate_work
# ** Error: (vsim-3033) Instantiation of 'CARRY_COUT_PLUG' failed. The design unit was not found.
#    Time: 0 ps  Iteration: 0  Instance: /tb/dut File: top_post_synthesis.v Line: 1366
#         Searched libraries:
#             /home/vegg/Documents/FPGA/simulation/gate_work
#             /home/vegg/Documents/FPGA/simulation/gate_work
# ** Error: (vsim-3033) Instantiation of 'CE_VCC' failed. The design unit was not found.
#    Time: 0 ps  Iteration: 0  Instance: /tb/dut File: top_post_synthesis.v Line: 1372
#         Searched libraries:
#             /home/vegg/Documents/FPGA/simulation/gate_work
#             /home/vegg/Documents/FPGA/simulation/gate_work
# ** Error: (vsim-3033) Instantiation of 'CE_VCC' failed. The design unit was not found.
#    Time: 0 ps  Iteration: 0  Instance: /tb/dut File: top_post_synthesis.v Line: 1377
#         Searched libraries:
#             /home/vegg/Documents/FPGA/simulation/gate_work
#             /home/vegg/Documents/FPGA/simulation/gate_work
# ** Error: (vsim-3033) Instantiation of 'CE_VCC' failed. The design unit was not found.
#    Time: 0 ps  Iteration: 0  Instance: /tb/dut File: top_post_synthesis.v Line: 1382
#         Searched libraries:

`timescale 1ps/1ps
module tb();
localparam CLOCK_PERIOD = 8000;
localparam CLOCK_DELAY = CLOCK_PERIOD / 2;
//Simulation clock
logic sim_clk;
reg CLKT;
wire[0:3] LED;
//Instantiate the dut
top dut ( .clkT(sim_clk) , .led(LED));
//Load the SDF
initial $sdf_annotate("top_post_synthesis.sdf", dut);
//The simulation clock
initial sim_clk = '1;
always #CLOCK_DELAY sim_clk = ~sim_clk;
// //Randomized input
// always@(posedge sim_clk) begin
  
// end
endmodule