Hello, I am using a Zynq 7000 card and I made a design completely in the PL, it includes a clock signal, it is basically a register that with certain clock pulses lights an LED. What happens is that once the bitstream is generated, it gives me the warning that I write at the end, and when programming the card it does not do what it has to do. I do not know if it is because of that warning because I have the restrictions and I use the PL clock.

[DRC 23-20] Rule violation (ZPS7-1) PS7 block required - The PS7 cell must be used in this Zynq design in order to enable correct default configuration.