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sim.pysim: use "bench" as a top level root for testbench signals. #664

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merged 1 commit into from Dec 16, 2021
Merged

sim.pysim: use "bench" as a top level root for testbench signals. #664

merged 1 commit into from Dec 16, 2021

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Lunaphied
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Fixes #561.

@Lunaphied Lunaphied changed the title sim.pysim: use "testbench" as a top level root for testbench signals. sim.pysim: use "bench" as a top level root for testbench signals. Dec 16, 2021
whitequark
whitequark previously approved these changes Dec 16, 2021
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LGTM

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codecov-commenter commented Dec 16, 2021 •
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Codecov Report

Merging #664 (8028e98) into main (b1f5664) will not change coverage.
The diff coverage is 50.00%.

❗ Current head 8028e98 differs from pull request most recent head 7dcd3d3. Consider uploading reports for the commit 7dcd3d3 to get more accurate results
Impacted file tree graph

@@           Coverage Diff           @@
##             main     #664   +/-   ##
=======================================
  Coverage   81.48%   81.48%           
=======================================
  Files          49       49           
  Lines        6475     6475           
  Branches     1533     1533           
=======================================
  Hits         5276     5276           
  Misses       1007     1007           
  Partials      192      192
Impacted Files Coverage Δ
amaranth/sim/pysim.py 93.17% <50.00%> (ø)

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@whitequark whitequark merged commit 538c141 into amaranth-lang:main Dec 16, 2021
@Lunaphied Lunaphied deleted the fix-561 branch December 17, 2021 01:05
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Successfully merging this pull request may close these issues.

pysim: testbench-only signals are not placed at root level on the VCD file
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@Lunaphied @codecov-commenter @whitequark