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base repository: amaranth-lang/amaranth
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head repository: amaranth-lang/amaranth
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compare: 66295fa388be
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Dec 11, 2021

  1. sim.pysim: refuse to write VCD files with whitespace in signal names. 

    Closes #595.
    @whitequark
    whitequark committed Dec 11, 2021
    Copy the full SHA
    66295fa View commit details
Showing with 20 additions and 2 deletions.
  1. +5 −0 amaranth/sim/pysim.py
  2. +15 −2 tests/test_sim.py
5 changes: 5 additions & 0 deletions amaranth/sim/pysim.py
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
from contextlib import contextmanager
import itertools
import re
from vcd import VCDWriter
from vcd.gtkw import GTKWSave

@@ -94,6 +95,10 @@ def __init__(self, fragment, *, vcd_file, gtkw_file=None, traces=()):
var_init = signal.reset

for (*var_scope, var_name) in names:
if re.search(r"[ \t\r\n]", var_name):
raise NameError("Signal '{}.{}' contains a whitespace character"
.format(".".join(var_scope), var_name))

suffix = None
while True:
try:
17 changes: 15 additions & 2 deletions tests/test_sim.py
View file
Original file line number Diff line number Diff line change
@@ -806,8 +806,9 @@ def test_vcd_wrong_nonzero_time(self):
sim.run_until(1e-5)
with self.assertRaisesRegex(ValueError,
r"^Cannot start writing waveforms after advancing simulation time$"):
with sim.write_vcd(open(os.path.devnull, "wt")):
pass
with open(os.path.devnull, "w") as f:
with sim.write_vcd(f):
pass


class SimulatorRegressionTestCase(FHDLTestCase):
@@ -827,3 +828,15 @@ def process():
self.assertEqual((yield -(Const(0b11, 2).as_signed())), 1)
sim.add_process(process)
sim.run()

def test_bug_595(self):
dut = Module()
with dut.FSM(name="name with space"):
with dut.State(0):
pass
sim = Simulator(dut)
with self.assertRaisesRegex(NameError,
r"^Signal 'top\.name with space_state' contains a whitespace character$"):
with open(os.path.devnull, "w") as f:
with sim.write_vcd(f):
sim.run()