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base repository: amaranth-lang/amaranth
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  • 1 commit
  • 3 files changed
  • 1 contributor

Commits on Dec 11, 2021

  1. sim._pyrtl: reject very large values. 

    A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.

This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.

Fixes #588.
    @whitequark
    whitequark committed Dec 11, 2021
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