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@hellow554 It is simply very slow, as a << b generates a 4294967327 bit wide intermediate wire. Converting this to verilog / rtlil already catches this.
Maybe a similar check should be added to the simulator backend.
The following code does not complete (at least not in 1 minute, so I call it infinite ;) )
The problem seems to be the
a << b
operation.The text was updated successfully, but these errors were encountered: