back.rtlil: avoid sync process emission in RTLIL. #667
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We continue to emit combinatorial processes in RTLIL. This allows switch statements in the HDL itself to be mapped to switch statements in RTLIL, getting translated to Verilog case statements. This output has much higher clarity than using `$mux` cells directly. Fixes amaranth-lang#603.
Codecov Report
@@ Coverage Diff @@
## main #667 +/- ##
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- Coverage 81.48% 81.32% -0.16%
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Files 49 49
Lines 6475 6464 -11
Branches 1533 1526 -7
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- Hits 5276 5257 -19
- Misses 1007 1014 +7
- Partials 192 193 +1
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Avoiding emission of sync processes in RTLIL allows us to avoid a dependency on matching the behavior expected by Yosys, which generally expects sync processes in RTLIL to match those emitted by the output from it's own Verilog parser. This also simplifies the logic used in emitting RTLIL overall.
Combinatorial processes are still emitted however. Without these the RTLIL does not have a high-level understanding of
Switchstatements, which significantly diminishes the quality of emitted Verilog, as these are converted to$muxcells in Yosys, which become?constructs when converted back to Verilog.Fixes #603.