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If you use the internal oscillator, you can choose a 12.5, 25, 50, or 100 MHz clock under the Device and Pin Options
dialog box, in the Configuration page of the Intel Quartus Prime software.
It's not entirely clear where this adds a divider in the clocking path, so this needs to be checked.
The setting in question controls set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_{100,50,25,12_5}MHZ, which I think controls the oscillator frequency when loading bitstreams from flash.
More specifically: it changes the OPTION_REG_EXTERNAL_CLK_SPI part of bitstream Option RAM to 001 (100MHz) / 011 (50MHz) / 101 (25MHz) / 111 (12.5MHz). (this has been added to Mistral, since it was overlooked)
I think one would need to manually instantiate a cyclonev_oscillator block.
This needs to actually be measured on real hardware, value is not well documented.
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