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Undriven signal ends up as module port #630
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You're really supposed to provide an explicit port list iirc. from nmigen import *
from nmigen.back import verilog
class Test(Elaboratable):
def __init__(self):
self.val_out = Signal()
def elaborate(self, platform):
m = Module()
int_sig = Signal(8)
m.d.comb += self.val_out.eq(int_sig)
return m
if __name__ == "__main__":
top = Test()
with open("test.v", "w") as f:
f.write(verilog.convert(top, ports=[top.val_out])) /* Generated by Yosys 0.9+3755 (git sha1 442d19f6, clang 12.0.0 -fPIC -Os) */
(* \nmigen.hierarchy = "top" *)
(* top = 1 *)
(* generator = "nMigen" *)
module top(val_out);
wire [7:0] int_sig;
output val_out;
assign int_sig = 8'h00;
assign val_out = 1'h0;
endmodule |
Thanks @BracketMaster, that does fix the issue at the top level. I think there are a couple of usability issues here:
|
Let's deprecate optional |
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If a signal has no driver, it ends up as a port:
This is pretty confusing. Reporting an error here would be great.
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