Support platform specific output in a single file #657
Labels
Comments
|
So I think this already isn't particularly hard; you do need to specify the device (and so subclass the platform) but the amount of code to do that is minimal. The requirement to specify the exact device to get an from amaranth import *
from amaranth.lib.cdc import FFSynchronizer
from amaranth.back.verilog import convert
from amaranth.vendor.xilinx import XilinxPlatform
class _MyPlatform(XilinxPlatform):
device = "xc6slx9"
package = "tqg144"
speed = "2"
connectors = []
resources = []
class Foo(Elaboratable):
def __init__(self):
self.i = Signal()
self.o = Signal()
def elaborate(self, platform):
m = Module()
m.submodules += FFSynchronizer(self.o, self.i)
return m
print(convert(Foo(), platform=_MyPlatform()))/* Generated by Yosys 0.14+42 (git sha1 158600004, ccache clang 11.0.1-2 -O0 -fPIC) */
(* \amaranth.hierarchy = "top.U$$0" *)
(* generator = "Amaranth" *)
module \U$$0 (rst, clk, o);
(* src = "/home/whitequark/Projects/amaranth/amaranth/hdl/ir.py:527" *)
input clk;
wire clk;
(* src = "/home/whitequark/Projects/amaranth/x.py:18" *)
wire i;
(* src = "/home/whitequark/Projects/amaranth/x.py:19" *)
input o;
wire o;
(* src = "/home/whitequark/Projects/amaranth/amaranth/hdl/ir.py:527" *)
input rst;
wire rst;
(* ASYNC_REG = "TRUE" *)
(* src = "/home/whitequark/Projects/amaranth/amaranth/vendor/xilinx.py:1170" *)
reg stage0 = 1'h0;
(* src = "/home/whitequark/Projects/amaranth/amaranth/vendor/xilinx.py:1170" *)
wire \stage0$next ;
(* ASYNC_REG = "TRUE" *)
(* src = "/home/whitequark/Projects/amaranth/amaranth/vendor/xilinx.py:1170" *)
reg stage1 = 1'h0;
(* src = "/home/whitequark/Projects/amaranth/amaranth/vendor/xilinx.py:1170" *)
wire \stage1$next ;
always @(posedge clk)
stage0 <= \stage0$next ;
always @(posedge clk)
stage1 <= \stage1$next ;
assign i = stage1;
assign \stage1$next = stage0;
assign \stage0$next = o;
endmodule
(* \amaranth.hierarchy = "top" *)
(* top = 1 *)
(* generator = "Amaranth" *)
module top(rst, clk, o);
(* src = "/home/whitequark/Projects/amaranth/amaranth/hdl/ir.py:527" *)
input clk;
wire clk;
(* src = "/home/whitequark/Projects/amaranth/x.py:19" *)
input o;
wire o;
(* src = "/home/whitequark/Projects/amaranth/amaranth/hdl/ir.py:527" *)
input rst;
wire rst;
\U$$0 \U$$0 (
.clk(clk),
.o(o),
.rst(rst)
);
endmodule |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
One use of Amaranth that I frequently hit is just using it to produce a single output Verilog file that gets fed into another larger project. Currently this means that I directly convert the output to Verilog. What this means is that none of the platform specific changes such as
FFSynchronizerspecialization occur.This means that you can end up with extremely undesirable behavior such as synchronizers getting converted into shift registers since they will lack the attributes required to inform the Xilinx synthesis to not do this.
It should be significantly easier to produce this platform/device specific output without a full board configuration and/or producing an entire output project.
The text was updated successfully, but these errors were encountered: