Regarding ResetInserter: I think that's OK. We have a reset_less argument for FFSynchronizer and it's currently True so it's not affected, but in any case, if an outer module explicitly wants to reset something and the inner one opts into it by specifying reset_less=False then that should happen.

Regarding EnableInserter: I think that's also OK. Yes, randomly wrapping RTL with EnableInserter can break it. The purpose of EnableInserter is really clock gating conversion; you can't easily insert clock gates in FPGA designs but you can easily insert enable controls, so any time you want to gate the clock on a subset of cycles you use that. So the same thing happening with FFSynchronizer is expected and reasonable, I think.