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back.{rtlil,verilog}: deprecate implicit ports. #658

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merged 1 commit into from Dec 13, 2021

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Lunaphied
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Fixes #630.

@Lunaphied Lunaphied force-pushed the deprecate-ports branch 2 times, most recently from 4f5f72b to fb06005 Compare December 13, 2021 12:10
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codecov-commenter commented Dec 13, 2021

Codecov Report

Merging #658 (456449a) into main (24c4da2) will decrease coverage by 0.05%.
The diff coverage is 66.66%.

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@@            Coverage Diff             @@
##             main     #658      +/-   ##
==========================================
- Coverage   81.53%   81.48%   -0.06%     
==========================================
  Files          49       49              
  Lines        6467     6475       +8     
  Branches     1531     1533       +2     
==========================================
+ Hits         5273     5276       +3     
- Misses       1003     1005       +2     
- Partials      191      194       +3     
Impacted Files Coverage Δ
amaranth/back/rtlil.py 79.81% <50.00%> (-0.69%) ⬇️
amaranth/back/verilog.py 65.62% <75.00%> (+6.36%) ⬆️

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LGTM

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Undriven signal ends up as module port
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